A four-variable Boolean function is realized using
4 $$ \times $$ 1
multiplexers as shown in the
figure.
The minimized expression for F(U, V, W, X)
is
A
$$\left( {UV + \overline U \overline V } \right)\overline W $$
B
$$\left( {UV + \overline U \overline V } \right)\left( {\overline W \overline X + \overline W X} \right)$$
C
$$\left( {U\overline V + \overline U V} \right)\overline W $$
D
$$\left( {U\overline V + \overline U V} \right)\left( {\overline W \overline X + \overline W X} \right)$$
2
GATE ECE 2017 Set 2
Numerical
+2
-0
Figure I shows a 4-bits ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (FA). The
propagation delay of the XOR, AND and OR gates in Figure II are 20 ns, 15 ns and 10 ns respectively. Assume all the inputs to
the 4-bit adder are initially reset to 0.
At t=0, the inputs to the 4-bit adder are changed to $${X_3}$$$${X_2}$$$${X_1}$$$${X_0}$$ =1100, $${Y_3}$$$${Y_2}$$$${Y_1}$$$${Y_0}$$ = 0100 and $${Z_0}$$=1.
The output of the ripple carry adder will be stable at t (in ns) = ____
Your input ____
3
GATE ECE 2017 Set 2
MCQ (Single Correct Answer)
+2
-0.6
A programmable logic array (PLA) is shown in the figure.
The Boolean function F implemented is
A
$$\overline P \,\overline {Q\,} R + \overline P QR + P\overline {Q\,} \overline R $$
B
$$(\overline P \, + \overline {Q\,} + \,R)(\overline P \, + Q + R) + (P + \overline P \, + \overline R )$$
C
$$\overline P \,\overline {Q\,} R + \overline P QR + P\overline {Q\,} \,\overline R $$
D
$$(\overline P + \,\overline {Q\,} \, + R)(\overline P + Q + R) + (P + \overline {Q\,} + R)$$
4
GATE ECE 2016 Set 1
MCQ (Single Correct Answer)
+2
-0.6
The functionality implemented by the circuit below is
At t=0, the inputs to the 4-bit adder are changed to $${X_3}$$$${X_2}$$$${X_1}$$$${X_0}$$ =1100, $${Y_3}$$$${Y_2}$$$${Y_1}$$$${Y_0}$$ = 0100 and $${Z_0}$$=1.
The output of the ripple carry adder will be stable at t (in ns) = ____
The Boolean function F implemented is 