1
GATE ECE 2018
MCQ (Single Correct Answer)
+2
-0.67
A four-variable Boolean function is realized using 4 $$ \times $$ 1 multiplexers as shown in the figure. GATE ECE 2018 Digital Circuits - Combinational Circuits Question 2 English
The minimized expression for F(U, V, W, X) is
A
$$\left( {UV + \overline U \overline V } \right)\overline W $$
B
$$\left( {UV + \overline U \overline V } \right)\left( {\overline W \overline X + \overline W X} \right)$$
C
$$\left( {U\overline V + \overline U V} \right)\overline W $$
D
$$\left( {U\overline V + \overline U V} \right)\left( {\overline W \overline X + \overline W X} \right)$$
2
GATE ECE 2017 Set 2
MCQ (Single Correct Answer)
+2
-0.6
A programmable logic array (PLA) is shown in the figure. GATE ECE 2017 Set 2 Digital Circuits - Combinational Circuits Question 16 English The Boolean function F implemented is
A
$$\overline P \,\overline {Q\,} R + \overline P QR + P\overline {Q\,} \overline R $$
B
$$(\overline P \, + \overline {Q\,} + \,R)(\overline P \, + Q + R) + (P + \overline P \, + \overline R )$$
C
$$\overline P \,\overline {Q\,} R + \overline P QR + P\overline {Q\,} \,\overline R $$
D
$$(\overline P + \,\overline {Q\,} \, + R)(\overline P + Q + R) + (P + \overline {Q\,} + R)$$
3
GATE ECE 2017 Set 2
Numerical
+2
-0
Figure I shows a 4-bits ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure II are 20 ns, 15 ns and 10 ns respectively. Assume all the inputs to the 4-bit adder are initially reset to 0. GATE ECE 2017 Set 2 Digital Circuits - Combinational Circuits Question 15 English 1 GATE ECE 2017 Set 2 Digital Circuits - Combinational Circuits Question 15 English 2 At t=0, the inputs to the 4-bit adder are changed to $${X_3}$$$${X_2}$$$${X_1}$$$${X_0}$$ =1100, $${Y_3}$$$${Y_2}$$$${Y_1}$$$${Y_0}$$ = 0100 and $${Z_0}$$=1. The output of the ripple carry adder will be stable at t (in ns) = ____
Your input ____
4
GATE ECE 2016 Set 3
Numerical
+2
-0
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are 2 ns, 1.5 ns and 1 ns, respectively. If all the inputs P, Q, R, S and T are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is ___________. GATE ECE 2016 Set 3 Digital Circuits - Combinational Circuits Question 17 English
Your input ____
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