1
GATE ECE 2008
MCQ (Single Correct Answer)
+2
-0.6
For the circuit shown in the following figure $${I_0}$$ - $${I_3}$$ are inputs to the 4:1 multiplexer R(MSB) and S are control bits. tHE OUTPUT Zcan be represented by
2
GATE ECE 2007
MCQ (Single Correct Answer)
+2
-0.6
In the following circuit, X is given by


3
GATE ECE 2004
MCQ (Single Correct Answer)
+2
-0.6
The minimum number of 2 to 1 multiplexers required to realize a 4 to 1 mutliplexer is
4
GATE ECE 2003
MCQ (Single Correct Answer)
+2
-0.6
The circuit shown in figure converts


GATE ECE Subjects
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General Aptitude
Network Theory
Microprocessors
Signals and Systems
Discrete Fourier Transform and Fast Fourier Transform Discrete Time Signal Fourier Series Fourier Transform Continuous Time Signal Laplace Transform Fourier Transform Representation of Continuous Time Signal Fourier Series Transmission of Signal Through Continuous Time LTI Systems Miscellaneous Sampling Continuous Time Linear Invariant System Discrete Time Linear Time Invariant Systems Discrete Time Signal Z Transform Transmission of Signal Through Discrete Time Lti Systems
Electromagnetics
Digital Circuits
Electronic Devices and VLSI
Control Systems
Communications
Engineering Mathematics