1
GATE ECE 2014 Set 3
MCQ (Single Correct Answer)
+2
-0.6
In the circuit shown, 𝑊𝑊 and 𝑌𝑌 are MSBs of the control inputs. The output 𝐹𝐹 is given by GATE ECE 2014 Set 3 Digital Circuits - Combinational Circuits Question 24 English
A
$$F = \,W\overline X + \overline W X + \overline Y \,\overline Z $$
B
$$F = \,W\overline X + \overline W X + \overline Y \,Z$$
C
$$F = \,W\overline X \,\overline Y + \overline W X\,\overline Y $$
D
$$F = \,(\overline W + \overline X )\,\,\overline Y \,\overline Z $$
2
GATE ECE 2014 Set 3
MCQ (Single Correct Answer)
+2
-0.6
If X and Y are inputs and the Difference (D = X – Y) and the Borrow (B) are the outputs, which one of the following diagrams implements a half-subtractor?
A
GATE ECE 2014 Set 3 Digital Circuits - Combinational Circuits Question 23 English Option 1
B
GATE ECE 2014 Set 3 Digital Circuits - Combinational Circuits Question 23 English Option 2
C
GATE ECE 2014 Set 3 Digital Circuits - Combinational Circuits Question 23 English Option 3
D
GATE ECE 2014 Set 3 Digital Circuits - Combinational Circuits Question 23 English Option 4
3
GATE ECE 2010
MCQ (Single Correct Answer)
+2
-0.6
The Boolean function realized by the logic circuit shown is GATE ECE 2010 Digital Circuits - Combinational Circuits Question 25 English
A
F=∑m(0,1,3,5,9,10,14)
B
F=∑m(2,3,5,7,8,12,13)
C
F=∑m(1,2,4,5,11,14,15)
D
F=∑m(2,3,5,7,8,9,12)
4
GATE ECE 2009
MCQ (Single Correct Answer)
+2
-0.6
What are the minimum number of 2-to 1 multiplexers required to generate a 2-input AND gate and a 2-input EX-OR gate?
A
1 and 2
B
1 and 3
C
1 and 1
D
2 and 2
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