1
GATE ECE 2017 Set 2
MCQ (Single Correct Answer)
+2
-0.6
A programmable logic array (PLA) is shown in the figure.
The Boolean function F implemented is
2
GATE ECE 2016 Set 1
MCQ (Single Correct Answer)
+2
-0.6
The functionality implemented by the circuit below is
3
GATE ECE 2016 Set 1
MCQ (Single Correct Answer)
+2
-0.6
Identify the circuit below.
4
GATE ECE 2016 Set 3
Numerical
+2
-0
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are 2 ns, 1.5 ns and 1 ns, respectively.
If all the inputs P, Q, R, S and T are applied at the same time instant,
the maximum propagation delay (in ns) of the circuit is ___________.
Your input ____
Questions Asked from Combinational Circuits (Marks 2)
Number in Brackets after Paper Indicates No. of Questions
GATE ECE 2024 (2)
GATE ECE 2018 (1)
GATE ECE 2017 Set 2 (2)
GATE ECE 2016 Set 1 (2)
GATE ECE 2016 Set 3 (1)
GATE ECE 2015 Set 2 (1)
GATE ECE 2014 Set 4 (2)
GATE ECE 2014 Set 3 (2)
GATE ECE 2010 (1)
GATE ECE 2009 (1)
GATE ECE 2008 (1)
GATE ECE 2007 (1)
GATE ECE 2004 (1)
GATE ECE 2003 (2)
GATE ECE 2001 (1)
GATE ECE 1999 (1)
GATE ECE Subjects
Network Theory
Control Systems
Electronic Devices and VLSI
Analog Circuits
Digital Circuits
Microprocessors
Signals and Systems
Representation of Continuous Time Signal Fourier Series Discrete Time Signal Fourier Series Fourier Transform Discrete Time Signal Z Transform Continuous Time Linear Invariant System Transmission of Signal Through Continuous Time LTI Systems Discrete Time Linear Time Invariant Systems Sampling Continuous Time Signal Laplace Transform Discrete Fourier Transform and Fast Fourier Transform Transmission of Signal Through Discrete Time Lti Systems Miscellaneous Fourier Transform
Communications
Electromagnetics
General Aptitude