1
GATE ECE 2017 Set 2
MCQ (Single Correct Answer)
+2
-0.6
A programmable logic array (PLA) is shown in the figure. GATE ECE 2017 Set 2 Digital Circuits - Combinational Circuits Question 20 English The Boolean function F implemented is
A
$$\overline P \,\overline {Q\,} R + \overline P QR + P\overline {Q\,} \overline R $$
B
$$(\overline P \, + \overline {Q\,} + \,R)(\overline P \, + Q + R) + (P + \overline P \, + \overline R )$$
C
$$\overline P \,\overline {Q\,} R + \overline P QR + P\overline {Q\,} \,\overline R $$
D
$$(\overline P + \,\overline {Q\,} \, + R)(\overline P + Q + R) + (P + \overline {Q\,} + R)$$
2
GATE ECE 2016 Set 1
MCQ (Single Correct Answer)
+2
-0.6
The functionality implemented by the circuit below is GATE ECE 2016 Set 1 Digital Circuits - Combinational Circuits Question 22 English
A
2-to-1 multiplexer
B
4-to-1 multiplexer
C
7-to-1 multiplexer
D
6-to-1 multiplexer
3
GATE ECE 2016 Set 1
MCQ (Single Correct Answer)
+2
-0.6
Identify the circuit below. GATE ECE 2016 Set 1 Digital Circuits - Combinational Circuits Question 23 English
A
Binary to Gray code converter
B
Binary to XS3 converter
C
Gray to Binary converter
D
XS3 to Binary converter
4
GATE ECE 2016 Set 3
Numerical
+2
-0
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are 2 ns, 1.5 ns and 1 ns, respectively. If all the inputs P, Q, R, S and T are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is ___________. GATE ECE 2016 Set 3 Digital Circuits - Combinational Circuits Question 21 English
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