In figure, the Boolean expression for the output in terms of inputs A, B and C when the clock ‘CK’ is high, is given by _______.

Among the digital IC-families-ECL, TTL and CMOS:

A logic family has threshold voltage $${V_T}$$= 2V, minimum guaranteed output high voltage $${V_{OH}}$$= 4V, minimum accepted input high voltage $${V_{IH}}$$ = 3V, maximum guaranteed output low voltage $${V_{OL}}$$ = 1V, and maximum accepted input low voltage N $${V_{IL}}$$ =1.5V. Its noise margin is

Fill in the blanks of the statements below concerning the following Logic Families:
Standard TTL (74XX), Low power TTL(74LXX) Low power schottky TTL(74LSXX), schottky TTL(74 SXXX), Emitter coupled Logic (ECL), CMOS

(a) Among the TTL Families, ________ family requires considerably less power than the standard TTL (74XX) and also has com parable proparation delay.
(b) Only the _______ family can operate over a wide range of power supply voltages.