1
GATE ECE 2020
MCQ (Single Correct Answer)
+2
-0.67
Using the incremental low frequency small - signal model of the MOS device, the Norton equivalent resistance of the following circuit is
2
GATE ECE 2020
MCQ (Single Correct Answer)
+2
-0.67
An enhancement MOSFET of threshold voltage 3 V is being used in the sample and hold circuit given below. Assume that the substrate of the MOS device is connected to -10 V . If the input voltage $v_1$ liesbetween $\pm 10 \mathrm{~V}$, the minimum and the maximum value of $v_G$ required for proper sampling and holding respectively, are
3
GATE ECE 2013
MCQ (Single Correct Answer)
+2
-0.6
The ac schematic of an NMOS common-source stage is shown in the figure below, where part of
the biasing circuits has been omitted for simplicity. For the n -channel MOSFET M, the
transconductance gm = 1 mA/V, and body effect and channel length modulation effect are to be
neglected. The lower cutoff frequency in Hz of the circuit is approximately at
4
GATE ECE 2006
MCQ (Single Correct Answer)
+2
-0.6
An n-channel depletion MOSFET has following two points on its ID - VGS curve:
(i)VGS = 0 at Id = 12 mA and
(ii)VGS = -6 Volts at Zo =$$\infty $$
Which of the following Q-points will give the highest transconductance gain for small signals?
GATE ECE Subjects
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General Aptitude
Network Theory
Microprocessors
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Discrete Fourier Transform and Fast Fourier Transform Discrete Time Signal Fourier Series Fourier Transform Continuous Time Signal Laplace Transform Fourier Transform Representation of Continuous Time Signal Fourier Series Transmission of Signal Through Continuous Time LTI Systems Miscellaneous Sampling Continuous Time Linear Invariant System Discrete Time Linear Time Invariant Systems Discrete Time Signal Z Transform Transmission of Signal Through Discrete Time Lti Systems
Electromagnetics
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Electronic Devices and VLSI
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Engineering Mathematics