In the circuit shown below, P and Q are the inputs. The logical function realized by the circuit shown below is

Consider the 2-bit multiplexer (MUX) shown in the figure. For OUTPUT to be the XOR of C and D, the values for A₀, A₁, A₂ and A₃ are ___________.

The propagation delays of the XOR gate, AND gate and multiplexer (MUX) in the circuit shown in the figure are $4 \mathrm{~ns}, 2 \mathrm{~ns}$ and 1 ns respectively.

If all the inputs $P, Q, R, S$ and $T$ are applied simultaneously and held constant, the maximum propagation delay of the circuit is

The figure below shows a multiplexer where $S_1$ and $S_0$ are the select lines, $I_0$ to $I_3$ are the input data lines, $E N$ is the enable line, and $F(P, Q, R)$ is the output. $F$ is