1
GATE ECE 2017 Set 2
+1
-0.3
Consider the circuit shown in the figure. The Boolean expression F implemented by the circuit is
A
$$\overline X \,\overline Y \,\overline Z + XY + \,\overline Y \,Z$$
B
$$\overline X \,Y\,\overline Z + XZ + \,\overline Y \,Z$$
C
$$\overline X \,Y\,\overline Z + XY + \,\overline Y \,Z$$
D
$$\overline X \,\overline Y \,\overline Z + XZ + \,\overline Y \,Z$$
2
GATE ECE 2016 Set 2
+1
-0.3
A 4:1 multiplexer is to be used for generating the output carry of a full adder. A and B are the bits to be added while đļin is the input carry and đļout is the output carry. A and B are to be used as the select bits with A being the more significant select bit. Which one of the following statements correctly describes the choice of signals to be connected to the inputs $${I_0}$$, $${I_1}$$, $${I_2 }$$ and $${I_3}$$ so that the output is C$$_{out}$$?
A
$${I_0} = 0,{I_0} = {C_{in}},\,{I_{2\,}} = {C_{in}}\,and\,{I_3} = I$$
B
$${I_0} = 1,\,{I_1}\, = {C_{in}},\,{I_{2\,}} = {C_{in}}\,and\,{I_3} = I$$
C
$${I_0} = {C_{in}},\,\,{I_{1\,}} = 0,\,{I_{2\,}} = 1and\,{I_3} = \,{C_{in}}$$
D
$${I_0} = 0,{I_1} = {C_{in}},\,{I_{2\,}} = \,2and\,{I_3} = {C_{in}}\,$$
3
GATE ECE 2014 Set 2
+1
-0.3
In a half-subtractor circuit with X and Y as inputs, the Borrow (M) and Difference (N = X - Y) are given by
A
$$M = X \oplus Y,N = XY$$
B
$$M = XY,\,\,N = X \oplus Y$$
C
$$M = \overline X Y,\,\,N = X \oplus Y$$
D
$$M = X\overline Y ,\,\,\,N = \overline {X \oplus Y}$$
4
GATE ECE 2012
+1
-0.3
The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of combinations for which the output is logic 1, is
A
4
B
6
C
8
D
10
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