In an N bit flash ADC, the analog voltage is fed simultaneously to 2^N− 1 comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source V_in(whose output is being converted to digital format) has a source resistance of 75 Ω as shown in the circuit diagram below and the input capacitance of each comparator is 8 pF. The input must settle to an accuracy of 1/2 LSB even for a full scale input change for properconversion. Assume that the time taken by the thermometer to binary encoder is negligible. If the flash ADC has 8 bit resolution, which one of the following alternatives is closest to the maximum sampling rate?

In the following circuit, the comparator output is logic “I” if V₁ > V₂ and is logic “0” otherwise. The D/A conversion is done as per the relation $$${V_{DAC}} = \sum\limits_{n = 0}^3 {{2^{n - 1}}{b_n}\,\,} Volts,$$$ where b₃(MSB), b₂, b₁ and b₀ (LSB) are the counter outputs.

The counter starts from the clear state.

The magnitude of the error between V_DAC and V_in at steady state in volts is

In the following circuit, the comparator output is logic “I” if V₁ > V₂ and is logic “0” otherwise. The D/A conversion is done as per the relation $$${V_{DAC}} = \sum\limits_{n = 0}^3 {{2^{n - 1}}{b_n}\,\,} Volts,$$$ where b₃(MSB), b₂, b₁ and b₀ (LSB) are the counter outputs.

The counter starts from the clear state.

The stable reading of the LED display is

In the digital-to-Analog converter circuit shown in the figure below,
$${V_{R\,}}\, = \,10V$$ and $$R\, = \,10k\Omega $$

The current i is