1
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
The output of the logic gate in figure is 
2
GATE ECE 1995
MCQ (Single Correct Answer)
+1
-0.3
The minimum number of NAND gates required to implement the Boolean function $$A + A\overline B $$ $$ + A\overline B C$$ is equal to
3
GATE ECE 1994
Fill in the Blanks
+1
-0
A ring oscillator consisting of 5 inverters is running at a frequency of 1.0 MH$$_z$$. The progagation delay per gate is ______
4
GATE ECE 1993
MCQ (Single Correct Answer)
+1
-0.3
For the logic circuit shown in Figure, the output is equal to
Questions Asked from Logic Gates (Marks 1)
Number in Brackets after Paper Indicates No. of Questions
GATE ECE 2023 (1)
GATE ECE 2016 Set 1 (1)
GATE ECE 2016 Set 3 (1)
GATE ECE 2015 Set 3 (1)
GATE ECE 2015 Set 2 (1)
GATE ECE 2014 Set 4 (1)
GATE ECE 2013 (1)
GATE ECE 2011 (1)
GATE ECE 2010 (2)
GATE ECE 2002 (1)
GATE ECE 2001 (1)
GATE ECE 2000 (1)
GATE ECE 1997 (1)
GATE ECE 1995 (1)
GATE ECE 1994 (1)
GATE ECE 1993 (2)
GATE ECE 1989 (1)
GATE ECE 1988 (5)
GATE ECE Subjects
Network Theory
Control Systems
Electronic Devices and VLSI
Analog Circuits
Digital Circuits
Microprocessors
Signals and Systems
Representation of Continuous Time Signal Fourier Series Discrete Time Signal Fourier Series Fourier Transform Discrete Time Signal Z Transform Continuous Time Linear Invariant System Transmission of Signal Through Continuous Time LTI Systems Discrete Time Linear Time Invariant Systems Sampling Continuous Time Signal Laplace Transform Discrete Fourier Transform and Fast Fourier Transform Transmission of Signal Through Discrete Time Lti Systems Miscellaneous Fourier Transform
Communications
Electromagnetics
General Aptitude