For the circuit shown below, the propagation delay of each NAND gate is 1 ns. The critical path delay, in ns, is __________ (rounded off to the nearest integer).

The output of the combinational circuit given below is

The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is

In the circuit shown, diodes $${D_1}$$ ,$${D_2}$$ and $${D_3}$$ are ideal, and the inputs $${E_1}$$ , $${E_2}$$ and $${E_3}$$ are “0 V” for logic ‘0’ and “10 V” for logic ‘1’. What logic gate does the circuit represent?