1
GATE ECE 2023
Numerical
+1
-0.33
For the circuit shown below, the propagation delay of each NAND gate is 1 ns. The critical path delay, in ns, is __________ (rounded off to the nearest integer).
Your input ____
2
GATE ECE 2016 Set 3
MCQ (Single Correct Answer)
+1
-0.3
The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is
3
GATE ECE 2016 Set 1
MCQ (Single Correct Answer)
+1
-0.3
The output of the combinational circuit given below is
4
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+1
-0.3
In the figure shown, the output ܻ is required to be ܻ Y=AB+ $$\overline C $$$$\overline D $$. The gates G1 and G2 must be,
respectively,
Questions Asked from Logic Gates (Marks 1)
Number in Brackets after Paper Indicates No. of Questions
GATE ECE 2023 (1)
GATE ECE 2016 Set 3 (1)
GATE ECE 2016 Set 1 (1)
GATE ECE 2015 Set 2 (1)
GATE ECE 2015 Set 3 (1)
GATE ECE 2014 Set 4 (1)
GATE ECE 2013 (1)
GATE ECE 2011 (1)
GATE ECE 2010 (2)
GATE ECE 2002 (1)
GATE ECE 2001 (1)
GATE ECE 2000 (1)
GATE ECE 1997 (1)
GATE ECE 1995 (1)
GATE ECE 1994 (1)
GATE ECE 1993 (2)
GATE ECE 1989 (1)
GATE ECE 1988 (5)
GATE ECE Subjects
Signals and Systems
Representation of Continuous Time Signal Fourier Series Discrete Time Signal Fourier Series Fourier Transform Discrete Time Signal Z Transform Continuous Time Linear Invariant System Transmission of Signal Through Continuous Time LTI Systems Discrete Time Linear Time Invariant Systems Sampling Continuous Time Signal Laplace Transform Discrete Fourier Transform and Fast Fourier Transform Transmission of Signal Through Discrete Time Lti Systems Miscellaneous Fourier Transform
Network Theory
Control Systems
Digital Circuits
General Aptitude
Electronic Devices and VLSI
Analog Circuits
Engineering Mathematics
Microprocessors
Communications
Electromagnetics