ExamSIDE (Powered by ExamGOAL)
Questions
PREVIOUS NEXT
1
GATE ECE 2003
MCQ (Single Correct Answer)
+2
-0.6
If the input to the ideal comparator shown in figure is sinusoidal signal of 8V (peak to peak) without any DC component, then the output of the comparator has a duty cycle of GATE ECE 2003 Analog Circuits - Operational Amplifier Question 51 English
A
1/2
B
1/3
C
1/6
D
1/12
2
GATE ECE 2003
MCQ (Single Correct Answer)
+2
-0.6
The output voltage of the Regulated power supply shown in the figure is GATE ECE 2003 Analog Circuits - Operational Amplifier Question 50 English
A
3 V
B
6 V
C
9 V
D
12 V
3
GATE ECE 2001
MCQ (Single Correct Answer)
+2
-0.6
In the figure assume the Op-Amps to be ideal. The output V0 of the circuit is GATE ECE 2001 Analog Circuits - Operational Amplifier Question 53 English
A
10 $$\cos $$ (100 t)
B
10 $$\int\limits_0^t {\cos \,\,\left( {100\tau } \right)} \,\,d\tau $$ v
C
$${10^{ - 4}}\int\limits_0^t {\cos \,\,\left( {100\tau } \right)} \,\,d\tau $$
D
$${10^{ - 4}}{d \over {dt}}\cos \left( {100t} \right)$$
4
GATE ECE 2001
MCQ (Single Correct Answer)
+2
-0.6
The Inverting Op-Amp shown in the figure, has an Open-loop gain of 100. The closed loop gain $${{{V_o}} \over {{V_s}}}$$ is GATE ECE 2001 Analog Circuits - Operational Amplifier Question 54 English
A
-8
B
-9
C
-10
D
-11
PREVIOUS NEXT
GATE ECE Subjects
Signals and Systems
Representation of Continuous Time Signal Fourier Series Fourier Transform Continuous Time Signal Laplace Transform Discrete Time Signal Fourier Series Fourier Transform Discrete Fourier Transform and Fast Fourier Transform Discrete Time Signal Z Transform Continuous Time Linear Invariant System Discrete Time Linear Time Invariant Systems Transmission of Signal Through Continuous Time LTI Systems Sampling Transmission of Signal Through Discrete Time Lti Systems Miscellaneous
Network Theory
State Equations For Networks Network Elements Network Theorems Two Port Networks Transient Response Sinusoidal Steady State Response Network Graphs Miscellaneous
Control Systems
Signal Flow Graph and Block Diagram Time Response Analysis Compensators Basic of Control Systems Frequency Response Analysis Stability Root Locus Diagram State Space Analysis
Digital Circuits
Logic Gates Boolean Algebra Analog to Digital and Digital to Analog Converters Sequential Circuits Combinational Circuits Logic Families Number System and Code Convertions Semiconductor Memories
General Aptitude
Numerical Ability Logical Reasoning Verbal Ability
Electronic Devices and VLSI
Semiconductor Physics PN Junction BJT and FET IC Basics and MOSFET
Analog Circuits
Diodes Bipolar Junction Transistor Frequency Response FET and MOSFET Oscillators Operational Amplifier Feedback Amplifier Power Amplifier 555 Timer
Engineering Mathematics
Linear Algebra Calculus Vector Calculus Probability and Statistics Differential Equations Complex Variable Numerical Methods Transform Theory
Microprocessors
Instruction Set and Programming with 8085 Pin Details of 8085 and Interfacing with 8085
Communications
Fundamentals of Information Theory Noise In Digital Communication Analog Communication Systems Digital Communication Systems Random Signals and Noise
Electromagnetics
Maxwell Equations Transmission Lines Uniform Plane Waves Waveguides Antennas Miscellaneous
EXAM MAP
Joint Entrance Examination
JEE MainJEE AdvancedWB JEEBITSATMHT CETKCETCOMEDKVITEEEAP EAPCET
Medical
NEETAIIMS
Graduate Aptitude Test in Engineering
GATE CSEGATE ECEGATE EEGATE MEGATE CEGATE PIGATE IN
Civil Services
UPSC Civil Service
Defence
NDA
Staff Selection Commission
SSC CGL Tier I
CBSE
Class 12