1
GATE ECE 2017 Set 1
Numerical
+2
-0
The amplifier circuit shown in the figure is implemented using a compensated operational amplifier (op-amp), and has an open-loop voltage gain, A0 105 V/V and an open-loop cut-off frequency, fC = 8 Hz. The voltage gain of the amplifier at 15 kHz, in V/V, is __________. GATE ECE 2017 Set 1 Analog Circuits - Operational Amplifier Question 11 English
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2
GATE ECE 2017 Set 2
Numerical
+2
-0
In the voltage reference circuit shown in the figure, the op-amp is ideal and the transistors Q1, Q2,….., Q32 are identical in all respects and have infinitely large values of common – emitter current gain $$\beta $$. The collector current (IC) of the transistors is related to their base emitter voltage (VBE) by the relation IC = IS exp (VBE/VT); where Is is the saturation current. Assume that the voltage VP shown in the figure is 0.7 V and the thermal voltage VT=26mV GATE ECE 2017 Set 2 Analog Circuits - Operational Amplifier Question 10 English

The output voltage Vout (in volts) is _____.

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3
GATE ECE 2016 Set 2
Numerical
+2
-0
In the opamp circuit shown, the Zener diodes Z1 and Z2 clamp the output voltage Vo to +5 V or -5 V. The switch S is intially closed and is opened at time t = 0 GATE ECE 2016 Set 2 Analog Circuits - Operational Amplifier Question 14 English

The time t = t1 (in seconds) at which Vo changes state is _____.

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4
GATE ECE 2016 Set 2
Numerical
+2
-0
An opamp has a finite open loop voltage gain of 100. Its input offset voltage Vios (= +5mV) is modeled as shown in the circuit below. The amplifier is ideal in all other respects. Vinput is 25 mV. GATE ECE 2016 Set 2 Analog Circuits - Operational Amplifier Question 13 English

The output voltage (in millivolts) is ________.

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