1
GATE ECE 2022
Numerical
+2
-0

Consider the circuit shown with an ideal long channel nMOSFET (enhancement mode, substrate is connected to the source). The transistor is appropriately biased in the saturation region with VGG and VDD such that it acts as a linear amplifier. vi is the small-signal ac input voltage. vA and vB represent the small-signal voltages at the nodes A and B, respectively. The value of $${{{v_A}} \over {{v_B}}}$$ is __________ (rounded off to one decimal place).

GATE ECE 2022 Analog Circuits - FET and MOSFET Question 14 English

Your input ____
2
GATE ECE 2021
MCQ (Single Correct Answer)
+2
-0.67

For an $n$-channel silicon MOSFET with 10 nm gate oxide thickness, the substrate sensitivity ( $\partial V_T / \partial\left|V_{B S}\right|$ ) is found to be $50 \mathrm{mV} / \mathrm{V}$ at a substrate voltage $\left|V_{B S}\right|=2 \mathrm{~V}$, where $V_T$ is the threshold voltage of the MOSFET. Assume that, $\left|V_{B S}\right| \gg 2 \phi_B$, where $q \phi_B$ is the separation between the Femi energy level $E_F$ and the intrinsic level $E_i$ in the bulk. Parameters given are

Electron charge $(q)=1.6 \times 10^{-9} \mathrm{C}$

Vacuum permittivity $\left(\varepsilon_o\right)=8.85 \times 10^{-12} \mathrm{~F} / \mathrm{m}$

Relative permittivity of silicon $\left(\varepsilon_{S i}\right)=12$

Relative permittivity of oxide $\left(\varepsilon_{o x}\right)=4$

The doping concentration of the substrate is

A

$2.37 \times 10^{15} \mathrm{~cm}^{-3}$

B

$4.37 \times 10^{15} \mathrm{~cm}^{-3}$

C

$9.37 \times 10^{15} \mathrm{~cm}^{-3}$

D

$7.37 \times 10^{15} \mathrm{~cm}^{-3}$

3
GATE ECE 2020
MCQ (Single Correct Answer)
+2
-0.67

Using the incremental low frequency small - signal model of the MOS device, the Norton equivalent resistance of the following circuit is

GATE ECE 2020 Analog Circuits - FET and MOSFET Question 3 English
A

$r_{d s}+R$

B

$\frac{r_{d s}+R}{1+g_m r_{d s}}$

C

$r_{d s}+R+g_m r_{d s} R$

D

$r_{d s}+\frac{1}{g_m}+R$

4
GATE ECE 2020
MCQ (Single Correct Answer)
+2
-0.67

An enhancement MOSFET of threshold voltage 3 V is being used in the sample and hold circuit given below. Assume that the substrate of the MOS device is connected to -10 V . If the input voltage $v_1$ liesbetween $\pm 10 \mathrm{~V}$, the minimum and the maximum value of $v_G$ required for proper sampling and holding respectively, are

GATE ECE 2020 Analog Circuits - FET and MOSFET Question 2 English

A

10 V and -10 V

B

13 V and -7 V

C

10 V and -13 V

D

3 V and -3 V

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