The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for
LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the
output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes are
intentionally shorted to implement “wired logic”. Such shorted nodes will be HIGH only if
the outputs of all the gates whose outputs are shorted are HIGH.
The number of distinct values of X3X2X1X0 (out of the 16 possible values) that give
𝑌 = 1 is _______.
Your input ____
2
GATE ECE 2015 Set 1
Numerical
+2
-0
All the logic gates shown in the figure have a propagation delay of 20 ns. Let A = C = 0 and B = 1
until time t = 0. At t = 0, all the inputs flip (i.e., A = C = 1 and B = 0) and remain in that state. For
t > 0, output Z = 1 for a duration (in ns) of ______________.
Your input ____
3
GATE ECE 2015 Set 1
MCQ (Single Correct Answer)
+2
-0.6
A 3-input majority gate is defined by the logic function M (a,b,c) = ab+bc+ca. Which one of
the following gates is represented by the function M$$\left( {\overline {M\left( {a,b,c} \right),} M\left( {a,b,\overline c } \right),c} \right)?$$
A
3-Input NAND gate
B
3-Input XOR gate
C
3-Input NOR gate
D
3-Input XNOR gate
4
GATE ECE 2015 Set 3
MCQ (Single Correct Answer)
+2
-0.6
A universal logic gate can implement any Boolean function by connecting sufficient number of
them appropriately. Three gates are shown.
