1
GATE ECE 1988
Subjective
+8
-0
The circuit shown below uses TTL flip-flops. The flip-flops are triggered at the negative transitions of the clock. It is desired that when M = 1 the circuit should function as an up-counter (in 8421 BCD) and when M=0, as a down-counter. Design the combinational circuit interposed between the flip-flops so that the circuit works as desired. (i.e. find F as a function of Q,$$\overline Q $$, M, $$\overline M $$). GATE ECE 1988 Digital Circuits - Sequential Circuits Question 9 English
2
GATE ECE 1988
Subjective
+8
-0
For the circuit shown in the figure below, sketch V0 against time. Assume that all flip-flops are reset to zero before the clock is applied. GATE ECE 1988 Digital Circuits - Sequential Circuits Question 8 English
3
GATE ECE 1987
Subjective
+8
-0
A 2-input up/down synchrconous counter using two toggle flip-flops is shown in Fig.1. The counter's sequence is to be controlled by the input M as follows:
For M=1, sequence of Q1, Q0 is ..00, 01, 10, 11, 00, 01.......
For M=0, sequence of Q1, Q0 is ..00, 11, 10, 01, 00, 11......

(a)Design the necessary feedback logic for T1 and T0.

(b)Realize the feesback logic using inverters and 4-input multiplexers only. Use Q1 and Q0 as the control inputs of the multiplexer with Q1 as the MSB.

GATE ECE 1987 Digital Circuits - Sequential Circuits Question 17 English
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