A new clocked "X-Y" flip-flop is defined with two inputs, X and Y in addition to the clock input. The flip-flop functions as follows:

If XY=00, the flip-flop changes stage with each clock pulse.

If XY=01, the flip-flop state Q becomes 1 with the next clock pulse.

If XY=10, the flip-flop state Q becomes 0 with the next clock pulse.

If XY=11, no change of state occurs with the clock pulse.

(a) Write the Truth table for the X-Y flip flop

(b) Write the Excitation table for the X-Y flip flop

(c) It is desired to convert a J-K flip flop into the X-Y flip flop by adding some external gates, if necessary. Draw a circuit to show how you will implement the X-Y flip-flop using a J-K flip-flop.

The circuit shown below uses TTL flip-flops. The flip-flops are triggered at the negative transitions of the clock. It is desired that when M = 1 the circuit should function as an up-counter (in 8421 BCD) and when M=0, as a down-counter. Design the combinational circuit interposed between the flip-flops so that the circuit works as desired. (i.e. find F as a function of Q,$$\overline Q $$, M, $$\overline M $$).

For the circuit shown in the figure below, sketch V₀ against time. Assume that all flip-flops are reset to zero before the clock is applied.

A 2-input up/down synchrconous counter using two toggle flip-flops is shown in Fig.1. The counter's sequence is to be controlled by the input M as follows:
For M=1, sequence of Q₁, Q₀ is ..00, 01, 10, 11, 00, 01.......
For M=0, sequence of Q₁, Q₀ is ..00, 11, 10, 01, 00, 11......

(a)Design the necessary feedback logic for T₁ and T₀.

(b)Realize the feesback logic using inverters and 4-input multiplexers only. Use Q₁ and Q₀ as the control inputs of the multiplexer with Q₁ as the MSB.