If XY=00, the flip-flop changes stage with each clock pulse.

If XY=01, the flip-flop state Q becomes 1 with the next clock pulse.

If XY=10, the flip-flop state Q becomes 0 with the next clock pulse.

If XY=11, no change of state occurs with the clock pulse.

(a) Write the Truth table for the X-Y flip flop

(b) Write the Excitation table for the X-Y flip flop

(c) It is desired to convert a J-K flip flop into the X-Y flip flop by adding some external gates, if necessary. Draw a circuit to show how you will implement the X-Y flip-flop using a J-K flip-flop.

_{0}against time. Assume that all flip-flops are reset to zero before the clock is applied.

For M=1, sequence of Q

_{1}, Q

_{0}is ..00, 01, 10, 11, 00, 01.......

For M=0, sequence of Q

_{1}, Q

_{0}is ..00, 11, 10, 01, 00, 11......

(a)Design the necessary feedback logic for T_{1} and T_{0}.

(b)Realize the feesback logic using inverters and 4-input multiplexers only. Use Q_{1} and Q_{0} as the control inputs of the multiplexer with Q_{1} as the MSB.