1
GATE ECE 2007
+2
-0.6
The circuit diagram of a standard TTL NOT gate is shown in the figure. When $${V_i}$$= 2.5V, the modes of operation of the transistors will be:
A

$${Q_1}$$ :reverse active

$${Q_2}$$; normal active

$${Q_3}$$; :saturation;

$${Q_4}$$ :cut-off

B

$${Q_1}$$ :reverse active

$${Q_2}$$: saturation

$${Q_3}$$: saturation

$${Q_4}$$ : cut-off

C

$${Q_1}$$ : normal active

$${Q_2}$$; cut-off

$${Q_3}$$; cut-off

$${Q_4}$$ : saturation

D

$${Q_1}$$ : :saturation

$${Q_2}$$: :saturation

$${Q_3}$$ :saturation

$${Q_4}$$ : normal active

2
GATE ECE 2003
+2
-0.6
The DTL, TTL, ECL and CMOS families of digital ICs are compared in the following 4 columns
A
P
B
Q
C
R
D
S
3
GATE ECE 1994
True or False
+2
-0
In the output stage of a standard TTL, we have a diode between the emitter of the pull up transistor and the collector of the pull-down transistor. The purpose of this diode is to isolate the output node from the power supply $${V_{cc}}$$.
A
TRUE
B
FALSE
4
GATE ECE 1987
+2
-0.6
Given that for a logic family,

$${V_{OH}}$$ is the minimum output high-level voltage
$${V_{OL}}$$ is the minimum output low-level voltage
$${V_{IH}}$$ is the minimum output high-level voltage and
$${V_{IL}}$$ is the minimum output low-level voltage.
The correct relationship is:

A
$${V_{IH}}$$ >$${V_{OH}}$$ >$${V_{IL}}$$ >$${V_{OL}}$$
B
$${V_{OH}}$$ > $${V_{IH}}$$> $${V_{IL}}$$ >$${V_{OL}}$$
C
$${V_{IH}}$$>$${V_{OH}}$$ >$${V_{OL}}$$ >$${V_{IL}}$$
D
$${V_{OH}}$$ > $${V_{IH}}$$>$${V_{OL}}$$ >$${V_{IL}}$$
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