1
GATE ECE 2023
Numerical
+2
-0.67

A sample and hold circuit is implemented using a resistive switch and a capacitor with a time constant of 1 $$\mu$$s. The time for the sampling switch to stay closed to charge a capacitor adequately to a full scale voltage of 1 V with 12-bit accuracy is ___________ $$\mu$$s (rounded off to two decimal places).

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2
GATE ECE 2022
MCQ (Single Correct Answer)
+2
-0.67

A circuit with an ideal OPAMP is shown. The Bode plot for the magnitude (in dB) of the gain transfer function (Av(j$$\omega$$) = Vout(j$$\omega$$)/Vin(j$$\omega$$)) of the circuit is also provided (here, $$\omega$$ is the angular frequency in rad/s). The values of R and C are __________.

GATE ECE 2022 Analog Circuits - Operational Amplifier Question 6 English

A
R = 3 k$$\Omega$$, C = 1 $$\mu$$F
B
R = 1 k$$\Omega$$, C = 3 $$\mu$$F
C
R = 4 k$$\Omega$$, C = 1 $$\mu$$F
D
R = 3 k$$\Omega$$, C = 2 $$\mu$$F
3
GATE ECE 2017 Set 2
Numerical
+2
-0
In the voltage reference circuit shown in the figure, the op-amp is ideal and the transistors Q1, Q2,….., Q32 are identical in all respects and have infinitely large values of common – emitter current gain $$\beta $$. The collector current (IC) of the transistors is related to their base emitter voltage (VBE) by the relation IC = IS exp (VBE/VT); where Is is the saturation current. Assume that the voltage VP shown in the figure is 0.7 V and the thermal voltage VT=26mV GATE ECE 2017 Set 2 Analog Circuits - Operational Amplifier Question 14 English

The output voltage Vout (in volts) is _____.

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4
GATE ECE 2017 Set 1
Numerical
+2
-0
The amplifier circuit shown in the figure is implemented using a compensated operational amplifier (op-amp), and has an open-loop voltage gain, A0 105 V/V and an open-loop cut-off frequency, fC = 8 Hz. The voltage gain of the amplifier at 15 kHz, in V/V, is __________. GATE ECE 2017 Set 1 Analog Circuits - Operational Amplifier Question 15 English
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