1
GATE ECE 2016 Set 2
Numerical
+2
-0
In the opamp circuit shown, the Zener diodes Z1 and Z2 clamp the output voltage Vo to +5 V or -5 V. The switch S is intially closed and is opened at time t = 0 GATE ECE 2016 Set 2 Analog Circuits - Operational Amplifier Question 18 English

The time t = t1 (in seconds) at which Vo changes state is _____.

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2
GATE ECE 2015 Set 3
Numerical
+2
-0
In the circuit shown, assume that the opamp is ideal. If the gain ($${V_0}/{V_{in}}$$) is -12, the value of R (in K$$\Omega $$) is _____. GATE ECE 2015 Set 3 Analog Circuits - Operational Amplifier Question 24 English
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3
GATE ECE 2015 Set 2
Numerical
+2
-0
Assuming that the op-amp in the circuit shown below is ideal, the output voltage V0 (in volts) GATE ECE 2015 Set 2 Analog Circuits - Operational Amplifier Question 25 English
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4
GATE ECE 2015 Set 2
Numerical
+2
-0
For the voltage regulator circuit shown, the input voltage (Vin) is 20V $$ \pm $$ 20% and the regulated output voltage (Vout) is 10 V. Assume the opamp to be ideal . For a load RL drawing 200 mA, the maximum power dissipation in Q1 (in Watts) is ______. GATE ECE 2015 Set 2 Analog Circuits - Operational Amplifier Question 26 English
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