1
GATE ECE 1988
Subjective
+8
-0
For the circuit shown in the figure below, sketch V0 against time. Assume that all flip-flops are reset to zero before the clock is applied.
2
GATE ECE 1987
Subjective
+8
-0
A 2-input up/down synchrconous counter using two toggle flip-flops is shown in Fig.1. The counter's sequence is to be controlled by the input M as follows:
For M=1, sequence of Q1, Q0 is ..00, 01, 10, 11, 00, 01.......
For M=0, sequence of Q1, Q0 is ..00, 11, 10, 01, 00, 11......
For M=1, sequence of Q1, Q0 is ..00, 01, 10, 11, 00, 01.......
For M=0, sequence of Q1, Q0 is ..00, 11, 10, 01, 00, 11......
(a)Design the necessary feedback logic for T1 and T0.
(b)Realize the feesback logic using inverters and 4-input multiplexers only. Use Q1 and Q0 as the control inputs of the multiplexer with Q1 as the MSB.
Questions Asked from Sequential Circuits (Marks 8)
Number in Brackets after Paper Indicates No. of Questions
GATE ECE Subjects
Network Theory
Control Systems
Electronic Devices and VLSI
Analog Circuits
Digital Circuits
Microprocessors
Signals and Systems
Representation of Continuous Time Signal Fourier Series Fourier Transform Continuous Time Signal Laplace Transform Discrete Time Signal Fourier Series Fourier Transform Discrete Fourier Transform and Fast Fourier Transform Discrete Time Signal Z Transform Continuous Time Linear Invariant System Discrete Time Linear Time Invariant Systems Transmission of Signal Through Continuous Time LTI Systems Sampling Transmission of Signal Through Discrete Time Lti Systems Miscellaneous
Communications
Electromagnetics
General Aptitude