1
GATE ECE 2015 Set 3
Numerical
+2
-0
An npn BJT having reverse saturation current $$I_s\;=\;10^{-15}\;A$$ is biased in the forward active region with VBE = 700 mV. The thermal voltage (VT) is 25 mV and the current gain (β) may vary from 50 to 150 due to manufacturing variations. The maximum emitter current (in μA) is _____.
2
GATE ECE 2014 Set 4
Numerical
+2
-0
Consider two BJT's biased at the same collector current with area A1 = 0.2 μm × 0.2 μm and A2 = 300 μm × 300 μm. Assuming that all other device parameters are identical, kT/q = 26 mV, the intrinsic carrier concentration is 1 × 1010 cm-3, and q = 1.6 × 10-19 C, the difference between the base-emitter voltages (in mV) of the two BJT's (i.e., VBE1 – VBE2) is___________.
3
GATE ECE 2011
+2
-0.6
The channel resistance of an N-channel JFET shown in the figure below is 600 W when the full channel thickness (tch) of 10 μm is available for conduction. The built-in voltage of the gate P+N junction (Vbi) is -1 V. When the gate to source voltage (VGS) is 0 V, the channel is depleted by 1 μm on each side due to the built in voltage and hence the thickness available for conduction is only 8 μm The channel resistance when VGS = -3 V is
A
360 Ω
B
917 Ω
C
1000 Ω
D
3000 Ω
4
GATE ECE 2011
+2
-0.6
The channel resistance of an N-channel JFET shown in the figure below is 600 W when the full channel thickness (tch) of 10 μm is available for conduction. The built-in voltage of the gate P+N junction (Vbi) is -1 V. When the gate to source voltage (VGS) is 0 V, the channel is depleted by 1 μm on each side due to the built in voltage and hence the thickness available for conduction is only 8 μm The channel resistance when VGS = 0 V is
A
480 Ω
B
600 Ω
C
750 Ω
D
1000 Ω
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