1
GATE ECE 2018
MCQ (Single Correct Answer)
+2
-0.67
A 2 $$ \times $$ 2 ROM array is built with the help of diodes as shown in the circuit below. Here W0 and W1 are signals that select the word lines and B0 and B1 are signals that are output of the sense amps based on the stored data corresponding to the bit lines during the read operation. GATE ECE 2018 Digital Circuits - Semiconductor Memories Question 1 English
During the read operation, the selected word line goes high and the other word line is in a high impedance state. As per the implementation shown in the circuit diagram above, what are the bits corresponding to Dij (where i = 0 or 1 and j = 0 or 1) stored in the ROM?
A
$$\left[ {\matrix{ 1 & 0 \cr 0 & 1 \cr } } \right]$$
B
$$\left[ {\matrix{ 0 & 1 \cr 1 & 0 \cr } } \right]$$
C
$$\left[ {\matrix{ 1 & 0 \cr 1 & 0 \cr } } \right]$$
D
$$\left[ {\matrix{ 1 & 1 \cr 0 & 0 \cr } } \right]$$
2
GATE ECE 2014 Set 3
MCQ (Single Correct Answer)
+2
-0.6
If WL is the Word Line and BL the Bit Line, an SRAM cell is shown in
A
GATE ECE 2014 Set 3 Digital Circuits - Semiconductor Memories Question 2 English Option 1
B
GATE ECE 2014 Set 3 Digital Circuits - Semiconductor Memories Question 2 English Option 2
C
GATE ECE 2014 Set 3 Digital Circuits - Semiconductor Memories Question 2 English Option 3
D
GATE ECE 2014 Set 3 Digital Circuits - Semiconductor Memories Question 2 English Option 4
3
GATE ECE 2003
MCQ (Single Correct Answer)
+2
-0.6
In the circuit shown in Figure, A is a parallel in, parallel-out 4-bit register, which loads at the rising edge of the clock C. The input lines are connected to a 4-bit bus, W. Its output acts as the input to a 16×4 ROM whose output is floating when the enable input E is 0. A partial table of the contents of the ROM is as follows GATE ECE 2003 Digital Circuits - Semiconductor Memories Question 3 English 1

The clock to the register is shown, and the data on the W bus at time t$$_1$$ is 0110. The data on the bus at time t$$_2$$ is

GATE ECE 2003 Digital Circuits - Semiconductor Memories Question 3 English 2 GATE ECE 2003 Digital Circuits - Semiconductor Memories Question 3 English 3
A
1111
B
1011
C
1000
D
0010
4
GATE ECE 2002
MCQ (Single Correct Answer)
+2
-0.6
If the input X$$_3$$, X$$_2$$, X$$_1$$, X$$_0$$ to the ROM in figure 2.12 are 8-4-2-1 BCD numbers, then the outpus are Y$$_3$$,Y$$_2$$, Y$$_1$$, Y$$_0$$ are GATE ECE 2002 Digital Circuits - Semiconductor Memories Question 4 English
A
gray code numbers
B
2-4-2-1 BCD numbers
C
excess-3 code numbeR
D
none of the above.
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