The circuit diagram of a synchronous counter is shown in the figure. Determine the sequence of states of the counter assuming that the initial state is ‘000’. Give your answer in a tabulor form showing the present state Q_A(n), Q_B(n), Q_C(n), J-K inputs ( J_A, K_A, J_B, K_B, J_C, K,) and the next state $${Q_{A\left( {n + 1} \right)}},\,{Q_{B\left( {n + 1} \right)}},{Q_{C\left( {n + 1} \right)}}$$ From the table, determine the modulus of the counter.

The mod-5 counter shown in figure counts through states Q₂ Q₁ Q₀ = 000, 001, 010, 011 and 100.

(a) Will the counter lockout if it happens to be in any one of the unused states?

(b) Find the maximum rate at which the counter will operate satisfactorily. Assume the propagation delays of flip-flop and AND gate to be t_F and t_A

A sequence generator is shown in figure. The counter status (Q₀ Q₁ Q₃) is intialized to 010 using preset/clear inputs.
The Clock has a period of 50ns and transitions take place at the rising clock edge.
(a) Give the sequence generated at Q₀ till it repeats.
(b) What is the repetition rate for the generated sequence?

A 4-bit shift register, which shifts 1 bit to the right at every clock pulse, is intialized to values (1000) for (Q₀Q₁Q₂Q₃). The D input is derived from Q₀, Q₂ and Q₃ through two XOR gates as shown in figure.

(a) Write the 4-bit values (Q₀Q₁Q₂Q₃) after each clock pulse till the pattern (1000) reappears on (Q₀Q₁Q₂Q₃).

(b) To what values should the shift register be intialized so that the pattern (1001) occurs after the first clock pulse?