1
GATE ECE 2013
MCQ (Single Correct Answer)
+2
-0.6
There are four chips each of 1024 bytes connected to a 16 bit address bus as shown in the figure below. RAMs 1,2,3 and 4 respectively are mapped to addresses GATE ECE 2013 Microprocessors - Pin Details of 8085 and Interfacing with 8085 Question 10 English
A
0C00H − 0FFFH,1C00H − 1FFFH, 2C00H − 2FFFH,3C00H − 3FFFH
B
1800H − 1FFFH,2800H − 2FFFH, 3800H − 3FFFH,4800H − 4FFFH
C
0500H − 08FFH,1500H − 18FFH, 3500H − 38FFH,5500H − 58FFH
D
0800H − 0BFFH,1800H − 1BFFH, 2800H − 2BFFH,3800H − 3BFFH
2
GATE ECE 2006
MCQ (Single Correct Answer)
+2
-0.6
An I/O peripheral device shown in figure (b) below is to be interfaced to an 8085 microprocessor. To select the I/O device in the I/O address range D4H – D7H, its chip-select (CS) should be connected to the output of the decoder shown in figure (a) below: GATE ECE 2006 Microprocessors - Pin Details of 8085 and Interfacing with 8085 Question 11 English
A
Output 7
B
Output 5
C
Output 2
D
Output 0
3
GATE ECE 2005
MCQ (Single Correct Answer)
+2
-0.6
What memory address range is NOT represented by chip 1 and chip 2 in figure? A0 to A15 in this figure are the address lines and CS means Chip Select. GATE ECE 2005 Microprocessors - Pin Details of 8085 and Interfacing with 8085 Question 12 English
A
0100H - 02FFH
B
1500H - 16FFH
C
F900H - FAFFH
D
F800H – F9FFH
4
GATE ECE 2004
MCQ (Single Correct Answer)
+2
-0.6
The 8255 Programmable Peripheral Interface is used as described below.

I. An A/D converter is interfaced to a microprocessor through an 8255. the conversion is initiated by a signal from the 8255 on Port C. A signal on Port C causes data to be strobed into Port A.

II. Two computers exchange data using a pair of 8255s. Port A works as a bidirectional data port supported by appropriate handshaking signals.

The appropriate modes of operation of the 8255 for I and II would be
A
Mode 0 for I and Mode 1 for II
B
Mode 1 for I and Mode 2 for II
C
Mode 2 for I and Mode 0 for II
D
Mode 2 for I and Mode 1 for II
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