1
GATE ECE 2016 Set 2
MCQ (Single Correct Answer)
+2
-0.6
An 8 Kbyte ROM with an active low Chip Select input CS is to be used in an 8085 microprocessor based system. The ROM should occupy the address range 1000H to 2FFFH. Theaddress lines are designated as A15 to A0, where A15is the most significant address bit.Which one of the following logicexpressions will generate the correct $$\overline{CS}$$ signal for this ROM?
A
$$A_{15}\;+\;A_{14}\;+\;(A_{13}.A_{12}+\overline{A_{13}}.\overline{A_{12}})$$
B
$$A_{15}.\;A_{14}.(A_{13}+A_{12})$$
C
$$\overline{A_{15}}.\;\overline{A_{14}}.(A_{13}.\overline{A_{12}}+\overline{A_{13}}.A_{12})$$
D
$$\overline{A_{15}}+\overline{A_{14}}+A_{13}A_{12}$$
2
GATE ECE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
For the 8085 microprocessor, the interfacing circuit to input 8-bit digital data (DI0 – DI7) from an external device is shown in the figure. The instruction for correct data transfer is GATE ECE 2014 Set 2 Microprocessors - Pin Details of 8085 and Interfacing with 8085 Question 9 English
A
MVI A, F8H
B
IN F8H
C
OUT F8H
D
LDA F8F8H
3
GATE ECE 2013
MCQ (Single Correct Answer)
+2
-0.6
There are four chips each of 1024 bytes connected to a 16 bit address bus as shown in the figure below. RAMs 1,2,3 and 4 respectively are mapped to addresses GATE ECE 2013 Microprocessors - Pin Details of 8085 and Interfacing with 8085 Question 10 English
A
0C00H − 0FFFH,1C00H − 1FFFH, 2C00H − 2FFFH,3C00H − 3FFFH
B
1800H − 1FFFH,2800H − 2FFFH, 3800H − 3FFFH,4800H − 4FFFH
C
0500H − 08FFH,1500H − 18FFH, 3500H − 38FFH,5500H − 58FFH
D
0800H − 0BFFH,1800H − 1BFFH, 2800H − 2BFFH,3800H − 3BFFH
4
GATE ECE 2006
MCQ (Single Correct Answer)
+2
-0.6
An I/O peripheral device shown in figure (b) below is to be interfaced to an 8085 microprocessor. To select the I/O device in the I/O address range D4H – D7H, its chip-select (CS) should be connected to the output of the decoder shown in figure (a) below: GATE ECE 2006 Microprocessors - Pin Details of 8085 and Interfacing with 8085 Question 11 English
A
Output 7
B
Output 5
C
Output 2
D
Output 0
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