1
GATE ECE 2016 Set 3
Numerical
+1
-0
The diodes D1 and D2 in the figure are ideal and the capacitors are identical. The product RC is very large compared to the time period of the ac voltage. Assuming that the diodes do not breakdown in the reverse bias, the output voltage V0 (in volt) at the steady state is__________. GATE ECE 2016 Set 3 Analog Circuits - Diodes Question 11 English
Your input ____
2
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+1
-0.3
If the circuit shown has to function as a clamping circuit, which one of the following conditions should be satisfied for sinusoidal signal of period T? GATE ECE 2015 Set 2 Analog Circuits - Diodes Question 13 English
A
RC << T
B
RC = 0.35 T
C
RC $$\approx$$ T
D
RC >> T
3
GATE ECE 2015 Set 3
Numerical
+1
-0
In the circuit shown, assume that diodes D1 and D2 are ideal. In the steady-state condition the average voltage Vab (in Volts) across the 0.5 μF capacitor is _____. GATE ECE 2015 Set 3 Analog Circuits - Diodes Question 15 English
Your input ____
4
GATE ECE 2014 Set 4
MCQ (Single Correct Answer)
+1
-0.3
For a given sample-and-hold circuit, if the value of the hold capacitor is increased, then
A
Droop rate decreases and acquisition time decreases
B
Droop rate decreases and acquisition time increases
C
Droop rate increases and acquisition time decreases
D
Droop rate increases and acquisition time increases
GATE ECE Subjects
EXAM MAP