1
GATE ECE 2016 Set 3
Numerical
+1
-0
The diodes D1 and D2 in the figure are ideal and the capacitors are identical. The product RC is very
large compared to the time period of the ac voltage. Assuming that the diodes do not breakdown in the
reverse bias, the output voltage V0 (in volt) at the steady state is__________.
Your input ____
2
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+1
-0.3
If the circuit shown has to function as a clamping circuit, which one of the following
conditions should be satisfied for sinusoidal signal of period T?
3
GATE ECE 2015 Set 3
Numerical
+1
-0
In the circuit shown, assume that diodes D1 and D2 are ideal. In the steady-state condition the average voltage Vab (in Volts) across the 0.5 μF capacitor is _____.
Your input ____
4
GATE ECE 2014 Set 4
MCQ (Single Correct Answer)
+1
-0.3
For a given sample-and-hold circuit, if the value of the hold capacitor is increased, then
Questions Asked from Diodes (Marks 1)
Number in Brackets after Paper Indicates No. of Questions
GATE ECE Subjects
Signals and Systems
Representation of Continuous Time Signal Fourier Series Fourier Transform Continuous Time Signal Laplace Transform Discrete Time Signal Fourier Series Fourier Transform Discrete Fourier Transform and Fast Fourier Transform Discrete Time Signal Z Transform Continuous Time Linear Invariant System Discrete Time Linear Time Invariant Systems Transmission of Signal Through Continuous Time LTI Systems Sampling Transmission of Signal Through Discrete Time Lti Systems Miscellaneous
Network Theory
Control Systems
Digital Circuits
General Aptitude
Electronic Devices and VLSI
Analog Circuits
Engineering Mathematics
Microprocessors
Communications
Electromagnetics