1
GATE ECE 2014 Set 4
MCQ (Single Correct Answer)
+1
-0.3
For a given sample-and-hold circuit, if the value of the hold capacitor is increased, then
A
Droop rate decreases and acquisition time decreases
B
Droop rate decreases and acquisition time increases
C
Droop rate increases and acquisition time decreases
D
Droop rate increases and acquisition time increases
2
GATE ECE 2014 Set 3
Numerical
+1
-0
The figure shows a half-wave rectifier. The diode D is ideal. The average steady-state current (in Amperes) through the diode is approximately ____________. GATE ECE 2014 Set 3 Analog Circuits - Diodes Question 13 English
Your input ____
3
GATE ECE 2012
MCQ (Single Correct Answer)
+1
-0.3
The diodes and capacitors in the circuit shown are ideal. The voltage v(t) across the diode D1 is GATE ECE 2012 Analog Circuits - Diodes Question 14 English
A
cos (ωt) − 1
B
sin (ωt)
C
1 - cos (ωt)
D
1 - sin (ωt)
4
GATE ECE 2003
MCQ (Single Correct Answer)
+1
-0.3
The circuit shown in figure is best described as a GATE ECE 2003 Analog Circuits - Diodes Question 15 English
A
bridge rectifier
B
ring modulator
C
frequency discriminator
D
voltage doubler
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