1
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+1
-0.3
If the circuit shown has to function as a clamping circuit, which one of the following
conditions should be satisfied for sinusoidal signal of period T?
2
GATE ECE 2014 Set 4
MCQ (Single Correct Answer)
+1
-0.3
For a given sample-and-hold circuit, if the value of the hold capacitor is increased, then
3
GATE ECE 2014 Set 3
Numerical
+1
-0
The figure shows a half-wave rectifier. The diode D is ideal. The average steady-state current
(in Amperes) through the diode is approximately ____________.
Your input ____
4
GATE ECE 2012
MCQ (Single Correct Answer)
+1
-0.3
The diodes and capacitors in the circuit shown are ideal. The voltage v(t)
across the diode D1 is
GATE ECE Subjects
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Network Theory
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Electronic Devices and VLSI
Analog Circuits
Digital Circuits
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Signals and Systems
Discrete Fourier Transform and Fast Fourier Transform Discrete Time Signal Fourier Series Fourier Transform Continuous Time Signal Laplace Transform Fourier Transform Representation of Continuous Time Signal Fourier Series Transmission of Signal Through Continuous Time LTI Systems Miscellaneous Sampling Continuous Time Linear Invariant System Discrete Time Linear Time Invariant Systems Discrete Time Signal Z Transform Transmission of Signal Through Discrete Time Lti Systems
Communications
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General Aptitude