1
GATE ECE 2015 Set 3
Numerical
+1
-0
In the circuit shown, assume that diodes D1 and D2 are ideal. In the steady-state condition the average voltage Vab (in Volts) across the 0.5 μF capacitor is _____. GATE ECE 2015 Set 3 Analog Circuits - Diodes Question 11 English
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2
GATE ECE 2015 Set 2
MCQ (Single Correct Answer)
+1
-0.3
If the circuit shown has to function as a clamping circuit, which one of the following conditions should be satisfied for sinusoidal signal of period T? GATE ECE 2015 Set 2 Analog Circuits - Diodes Question 9 English
A
RC << T
B
RC = 0.35 T
C
RC $$\approx$$ T
D
RC >> T
3
GATE ECE 2014 Set 4
MCQ (Single Correct Answer)
+1
-0.3
For a given sample-and-hold circuit, if the value of the hold capacitor is increased, then
A
Droop rate decreases and acquisition time decreases
B
Droop rate decreases and acquisition time increases
C
Droop rate increases and acquisition time decreases
D
Droop rate increases and acquisition time increases
4
GATE ECE 2014 Set 3
Numerical
+1
-0
The figure shows a half-wave rectifier. The diode D is ideal. The average steady-state current (in Amperes) through the diode is approximately ____________. GATE ECE 2014 Set 3 Analog Circuits - Diodes Question 13 English
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