1
GATE ECE 1999
MCQ (Single Correct Answer)
+1
-0.3
If $$CS\;=\overline{A_{15}}\;A_{14}\;A_{13}$$ is used as the chip select logic of a 4K RAM in an 8085 system, then its memory range will be
A
3000H – 3FFFH
B
7000H – 7FFFH
C
5000H – 5FFFH and 6000H – 6FFFH
D
6000H – 6FFFH and 7000H – 7FFFH
2
GATE ECE 1998
MCQ (Single Correct Answer)
+1
-0.3
An I/O processor control the flow of information between
A
cache memory and I/O devices
B
main memory and I/O devices
C
two I/O devices
D
cache and main memories
3
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
In an 8085$$\mu$$P system, the RST instruction will cause an interrupt
A
only if an interrupt service routine is not being executed
B
only if a bit in the interrupt mask is made 0
C
only if interrupts have been enabled by an EI instruction
D
None of the above
4
GATE ECE 1997
MCQ (Single Correct Answer)
+1
-0.3
The decoding circuit shown below has been used to generate the active low chip select signal for a microprocessor peripheral. (The address lines are designated as $${A_0}$$ to $${A_7}$$ for I-O address) GATE ECE 1997 Microprocessors - Pin Details of 8085 and Interfacing with 8085 Question 3 English
A
60 H to H
B
A 4 H to A7 H
C
50 H to AF H
D
70 H to 73 H
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