In the circuit shown below, $$V_1$$ and $$V_2$$ are bias voltages. Based on input and output impedances, the circuit behaves as a

Consider the CMOS circuit shown in the figure (substrates are connected to their respective sources). The gate width (W) to gate length (L) ratios $$\left( {{W \over L}} \right)$$ of the transistors are as shown. Both the transistors have the same gate oxide capacitance per unit area. For the pMOSFET, the threshold voltage is $$-$$1 V and the mobility of holes is $$40{{c{m^2}} \over {V.s}}$$. For the nMOSFET, the threshold voltage is 1 V and the mobility of electrons is $$300{{c{m^2}} \over {V.s}}$$. The steady state output voltage V₀ is ___________.

The ideal long channel nMOSFET and pMOSFET devices shown in the circuits have threshold voltages of 1 V and $$-$$1 V, respectively. The MOSFET substrates are connected to their respectively sources. Ignore leakage currents and assume that the capacitors are initially discharged. For the applied voltages as shown, the steady state voltages are ____________.

For the transistor $M_1$ in the circuit shown in the figure, $\mu_n C_{o x}=100 \mu \mathrm{~A} / V^2$ and $\frac{W}{L}=10$, where $\mu_n$ is the mobility of electron, $C_{o x}$ is the oxide capacitance per unit area. $W$ is the width and $L$ is the length.

The channel length modulation coefficient is ignored. If the gate-to-source voltage $V_{G S}$ is 1 V to keep the transistor at the edge of saturation. Then the threshold voltage of the transistor (rounded off to one decimal place) is $\_\_\_\_$ V.