1
GATE ECE 2022
MCQ (Single Correct Answer)
+1
-0.33

Consider the CMOS circuit shown in the figure (substrates are connected to their respective sources). The gate width (W) to gate length (L) ratios $$\left( {{W \over L}} \right)$$ of the transistors are as shown. Both the transistors have the same gate oxide capacitance per unit area. For the pMOSFET, the threshold voltage is $$-$$1 V and the mobility of holes is $$40{{c{m^2}} \over {V.s}}$$. For the nMOSFET, the threshold voltage is 1 V and the mobility of electrons is $$300{{c{m^2}} \over {V.s}}$$. The steady state output voltage V0 is ___________.

GATE ECE 2022 Analog Circuits - FET and MOSFET Question 1 English

A
equal to 0 V
B
more than 2 V
C
less than 2 V
D
equal to 2 V
2
GATE ECE 2022
MCQ (Single Correct Answer)
+1
-0.33

The ideal long channel nMOSFET and pMOSFET devices shown in the circuits have threshold voltages of 1 V and $$-$$1 V, respectively. The MOSFET substrates are connected to their respectively sources. Ignore leakage currents and assume that the capacitors are initially discharged. For the applied voltages as shown, the steady state voltages are ____________.

GATE ECE 2022 Analog Circuits - FET and MOSFET Question 4 English

A
V1 = 5 V, V2 = 5 V
B
V1 = 5 V, V2 = 4 V
C
V1 = 4 V, V2 = 5 V
D
V1 = 4 V, V2 = $$-$$5 V
3
GATE ECE 2022
MCQ (Single Correct Answer)
+1
-0.33

Consider an ideal long channel nMOSFET (enhancement-mode) with gate length 10 $$\mu$$m and width 100 $$\mu$$m. The product of electron mobility ($$\mu$$n) and oxide capacitance per unit area (Cox) is $$\mu$$nCox = 1 mA/V2. The threshold voltage of the transistor is 1 V. For a gate-to-source voltage VGS = [2 $$-$$ sin(2t)] V and drain-to source voltage VDS = 1 V (substrate connected to the source), the maximum value of the drain-to-source current is ___________.

A
40 mA
B
20 mA
C
15 mA
D
5 mA
4
GATE ECE 2022
Numerical
+1
-0.33

Consider the circuit shown with an ideal long channel nMOSFET (enhancement mode, substrate is connected to the source). The transistor is appropriately biased in the saturation region with VGG and VDD such that it acts as a linear amplifier. vi is the small-signal ac input voltage. vA and vB represent the small-signal voltages at the nodes A and B, respectively. The value of $${{{v_A}} \over {{v_B}}}$$ is __________ (rounded off to one decimal place).

GATE ECE 2022 Analog Circuits - FET and MOSFET Question 2 English

Your input ____
GATE ECE Subjects
EXAM MAP
Medical
NEET
Graduate Aptitude Test in Engineering
GATE CSEGATE ECEGATE EEGATE MEGATE CEGATE PIGATE IN
Civil Services
UPSC Civil Service
CBSE
Class 12