1
GATE CSE 2021 Set 1
+2
-0.67

Consider a 3-bit counter, designed using T flip-flop, as shown below:

Assuming the initial state of the counter given by PQR as 000, what are the next three states?

A
001, 010, 000
B
001, 010, 111
C
011, 101, 111
D
011, 101, 000
2
GATE CSE 2015 Set 1
+2
-0.6
A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.
A
0110110...
B
0100100...
C
011101110...
D
011001100...
3
GATE CSE 2014 Set 3
+2
-0.6

The above synchronous sequential circuit built using $$JK$$ flip-flops is initialized with $${Q_2}{Q_1}{Q_0} = 000.\,\,$$ The state sequence for this circuit for the next $$3$$ clock cycles is

A
$$001,010,011$$
B
$$111,110,101$$
C
$$100,110,111$$
D
$$100,011,001$$
4
GATE CSE 2011
+2
-0.6
Consider the following circuit involving three Dtypes flip-flops used in a certain type of Counter configuration.

If at some instance prior to the occurrence of the clock edge, $$P, Q$$ and $$R$$ have a value $$0,1$$ and $$0$$ respectively, what shall be the value of $$PQR$$ after the clock edge?

A
$$000$$
B
$$001$$
C
$$010$$
D
$$011$$
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Medical
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