A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipel...

Register renaming is done in pipelined processors

For a pipelined $$CPU$$ with a single $$ALU$$, consider the following situations $$1.\,\,\,\,\,$$ The $$j+1$$ instruction uses the result of the $$j$$...

Comparing the time $$T1$$ taken for a single instruction on a pipelined $$CPU$$ with time $$T2$$ taken on a non-pipelined but identical $$CPU,$$ we ca...

A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay...

Consider the following instruction sequence where register R1, R2 and R3 are general purpose and MEMORY[X] denotes the content at the memory location ...

Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline ...

The instruction pipeline of a $$RISC$$ processor has the following stages: Instruction Fetch $$(IF),$$ Instruction Decode $$(ID),$$ Operand Fetch $$(O...

Suppose the functions $$F$$ and $$G$$ can be computed in $$5$$ and $$3$$ nanoseconds by functional units $${U_F}$$ and $${U_G},$$ respectively. Given ...

Consider a $$3$$ $$GHz$$ (gigahertz) processor with a three-stage pipeline and stage latencies $${\tau _1},{\tau _2},$$ and $${\tau _3}$$ such that $$...

The stage delays in a $$4$$-stage pipeline are $$800, 500, 400$$ and $$300$$ picoseconds. The first stage (with delay $$800$$ picoseconds) is replaced...

Consider the following reservation table for a pipeline having three stages $${S_1},{S_2}$$ and $${S_3}.$$ The minimum average latency $$(MAL)$$ is ...

Consider the sequence of machine instructions given below: .tg {border-collapse:collapse;border-spacing:0;border:none;} .tg td{font-family:Arial, s...

Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a ...

Consider the following processors ($$ns$$ stands for nanoseconds). Assume that the pipeline registers have zero latency. $$P1:$$ Four-stage pipeline w...

An instruction pipeline has five stages, namely, instruction fetch $$(IF),$$ instruction decode and register fetch $$(ID/RF)$$ instruction execution $...

Consider a $$6$$-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When ...

Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction $$(FI),$$ Decode Instruction $$(DI),$$ Fetch Operan...

Consider an instruction pipeline with four stages $$\left( {S1,\,S2,\,S3,} \right.$$ and $$\left. {S4} \right)$$ each with combinational circuit only....

A $$5$$-stage pipelined processor has Instruction Fetch $$(IF),$$ Instruction Decode $$(ID),$$ Operand Fetch $$(OF),$$ Perform Operation $$(PO)$$ and ...

Consider a $$4$$ stage pipeline processor. The number of cycles needed by the four instructions $${\rm I}1,$$ $${\rm I}2,$$ $${\rm I}3,$$ $${\rm I}4,$...

The following code is to run on a pipelined processor with one branch delay slot $$\eqalign{ & {{\rm I}_1}:\,\,ADD\,\,{R_2}\,\, \leftarrow \,\,{...

In an instruction execution pipeline, the earliest that the data $$TLB$$ (Translation Look aside Buffer) can be accessed is

Which of the following are NOT true in a pipelined processor? $$1.$$ Bypassing can handle all RAW hazards $$2.$$ Register renaming can eliminate all r...

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for $$1.\,\,\,\,$$ Function locals and parameter...

Consider a pipelined processor with the following four stages $$\,\,\,\,\,$$$$IF:$$ Instruction Fetch $$\,\,\,\,\,$$$$ID:$$ Instruction Decode and Ope...

A CPU has five stages pipeline and runs at $$1$$ $$GHz$$ frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch...

A $$5$$ stage pipelined $$CPU$$ has the following sequence of stages $$IF$$-Instruction fetch from instruction memory, $$RD$$-Instruction decode and r...

A $$4$$-stage pipeline has the stage delays as $$150, 120,160$$ and $$140$$ nano seconds respectively. Registers that are used between the stages have...

The performance of a pipelined processor suffers if

An instruction pipeline has five stages where each stage takes $$2$$ nanoseconds and all instructions use all five stages. Branch instructions are not...

An instruction pipeline consists of $$4$$ stages: Fetch (F), Decode field (D), Execute (E), and Result-Write (W). The $$5$$ instructions in a certain ...