1
GATE CSE 2021 Set 2
MCQ (Single Correct Answer)
+2
-0.66

Suppose we want to design a synchronous circuit that processes a string of 0’s and 1’s. Given a string, it produces another string by replacing the first 1 in any subsequence of consecutive 1’s by a 0. Consider the following example.

Input sequence : 00100011000011100

Output sequence : 00000001000001100

A Mealy Machine is a state machine where both the next state and the output are functions of the present state and the current input.

The above mentioned circuit can be designed as a two-state Mealy machine. The states in the Mealy machine can be represented using Boolean values 0 and 1. We denote the current state, the next state, the next incoming bit, and the output bit of the Mealy machine by the variables s, t, b and y respectively.

Assume the initial state of the Mealy machine is 0.

What are the Boolean expressions corresponding to t and y in terms of s and b ?

A

t = b

y = sb

B

t = s + b

y = sb

C

t = s + b

y = sb̅

D

t = b

y = sb̅ 

2
GATE CSE 2021 Set 1
MCQ (Single Correct Answer)
+2
-0.67

Consider a 3-bit counter, designed using T flip-flop, as shown below:

GATE CSE 2021 Set 1 Digital Logic - Sequential Circuits Question 7 English

Assuming the initial state of the counter given by PQR as 000, what are the next three states?

A
001, 010, 000
B
001, 010, 111
C
011, 101, 111
D
011, 101, 000
3
GATE CSE 2015 Set 1
MCQ (Single Correct Answer)
+2
-0.6
A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.
A
0110110...
B
0100100...
C
011101110...
D
011001100...
4
GATE CSE 2014 Set 3
MCQ (Single Correct Answer)
+2
-0.6
GATE CSE 2014 Set 3 Digital Logic - Sequential Circuits Question 19 English

The above synchronous sequential circuit built using $$JK$$ flip-flops is initialized with $${Q_2}{Q_1}{Q_0} = 000.\,\,$$ The state sequence for this circuit for the next $$3$$ clock cycles is

A
$$001,010,011$$
B
$$111,110,101$$
C
$$100,110,111$$
D
$$100,011,001$$
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