1

GATE CSE 2014 Set 3

MCQ (Single Correct Answer)

+2

-0.6

The above synchronous sequential circuit built using $$JK$$ flip-flops is initialized with $${Q_2}{Q_1}{Q_0} = 000.\,\,$$ The state sequence for this circuit for the next $$3$$ clock cycles is

2

GATE CSE 2011

MCQ (Single Correct Answer)

+2

-0.6

Consider the following circuit involving three Dtypes flip-flops used in a certain type of Counter configuration.

If at some instance prior to the occurrence of the clock edge, $$P, Q$$ and $$R$$ have a value $$0,1$$ and $$0$$ respectively, what shall be the value of $$PQR$$ after the clock edge?

3

GATE CSE 2011

MCQ (Single Correct Answer)

+2

-0.6

Consider the following circuit involving three Dtypes flip-flops used in a certain type of Counter configuration.

If all the flip-flops were reset to $$0$$ at power on, what is the total number of distinct outputs (states) represented by $$PQR$$ generated by the counter?

4

GATE CSE 2009

MCQ (Single Correct Answer)

+2

-0.6

Given the following state table of an $$FSM$$ with two states $$A$$ and $$B,$$ one input and one output:

If the initial state is $$A = 0, B=0.$$ What is the minimum length of an input string which will take the machine to the state $$A=0, B=1$$ with Output$$=1?$$

Questions Asked from Sequential Circuits (Marks 2)

Number in Brackets after Paper Indicates No. of Questions

GATE CSE Subjects

Discrete Mathematics

Programming Languages

Theory of Computation

Operating Systems

Computer Organization

Database Management System

Data Structures

Computer Networks

Algorithms

Compiler Design

Software Engineering

Web Technologies

General Aptitude