Computer Arithmetic · Computer Organization · GATE CSE

The decimal value $$0.5$$ in $$IEEE$$ single precision floating point representation has

In the $$IEEE$$ floating point representation the hexadecimal value $$0\, \times \,00000000$$ corresponds to

What is the result of evaluating the following two expressions using three $$-$$ digit floating point arithmetic with rounding?
$$\eqalign{ & \left( {113. + - 111.} \right) + 7.51 \cr & 113. + \left( { - 111. + 7.51} \right) \cr} $$

In $$2’s$$ complement addition, the overflow

An $$N$$-bit carry look ahead adder, where $$N$$ is a multiple of $$4,$$ employs $${\rm I}cs$$ $$74181$$ ($$4$$bit $$ALU$$) and $$74182$$ ($$4$$ bit carry look ahead generator). The minimum addition time using the best architecture for this adder is

Both’s algorithm for integer multiplication gives worst performance when the multiplier pattern is

The value of a float type variable is represented using the single-precision $$32$$-bit floating point format of $$IEEE-754$$ standard that uses $$1$$ bit for sign, $$8$$ bits for biased exponent and $$23$$ bits for mantissa. $$A$$ float type variable $$X$$ is assigned the decimal value of $$−14.25.$$ The representation of $$X$$ in hexadecimal notation is

In a look $$-$$ ahead carry generator, the carry generate function $${G_i}$$ and the carry propagate function $${P_i}$$ for inputs, $${A_i}$$ and $${B_i}$$ are given by: $${P_i} = {A_i} \oplus {B_i}$$ and $${G_i} = {A_i}{B_i}.$$

The expressions for the sum bit $${S_i}$$ and the carry bit $${C_{i + 1}}$$ of the look ahead carry adder are given by $${S_i} = {P_i} \oplus {C_i}$$ and $${C_{i + 1}} = {G_i} + {P_i}{C_i},$$ where $${C_0}$$ is the input carry. Consider a two $$-$$ level logic implementation of the look $$-$$ ahead carry generator. Assume that all $${P_i}$$ and $${G_i}$$ are available for the carry generator circuit and that the $$AND$$ and $$OR$$ gates can have any number of inputs. The number of $$AND$$ gates and $$OR$$ gates needed to implement the look $$-$$ ahead carry generator for a $$4$$-bit adder with $${S_3},\,\,{S_2},\,\,{S_1},\,\,{S_0}$$ and $${C_4}$$ as its outputs are respectively

Given two three bit number $${a_2}{a_1}{a_0}$$ and $${b_2}{b_1}{b_0}$$ and $$c,$$ the carry in the function that represents the carry generate function when these two numbers are added is

The data given below. Solve the problems and choose the correct answer.

Mantissa is a pure fraction in sign - magnitude form. The decimal number $$0.239 \times {2^{13}}$$ has the following hexadecimal representation without normalization and rounding off

The data given below. Solve the problems and choose the correct answer.

The normalized representation for the above format is specified as follows. The mantissa has an implicit preceding the binary (radix) point. Assume that only $$0's$$ are padded in while shifting a field. The normalized representation of the above $$\left( {0.239 \times {2^{13}}} \right)$$ is

$$A$$ $$4$$-bit carry look ahead adder, which adds two $$4$$-bit numbers, is designed using $$AND,$$ $$OR,$$ $$NOT,$$ $$NAND,$$ $$NOR$$ gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level $$AND$$-$$OR$$ logic.

The following is a scheme for floating point number representation using $$16$$ bits.

Let $$s, e,$$ and $$m$$ be the numbers represented in binary in the sign, exponent, and mantissa fields respectively. Then the floating point number represented is

$$\left\{ {\matrix{ {{{\left( { - 1} \right)}^s}\left( {1 + m \times {2^{ - 9}}} \right){2^{e - 31}},} & {if\,the\,{\mathop{\rm exponent}\nolimits} \, \ne \,111111} \cr {\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,0} & {otherwise\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,} \cr } } \right.$$

What is the maximum difference between two successive real numbers representable in this system?

Sign extension is the step in

Booth’s coding in $$8$$ bits for the decimal number –$$57$$ is:

The number of full and half-adders required to add 16-bit numbers is:

Consider the following floating point number representation

The exponent is in $$2’s$$ complement representation and mantissa is in the sign magnitude representation. The range of the magnitude of the normalized mantissa in this representation is

State the Both's algorithm for multiplication of two numbers, Draw a block diagram for the implementation of the Booth's algorithm for determining the product of two $$8-$$bit signed numbers.