Memory Interfacing · Computer Organization · GATE CSE

Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a writ...

Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length...

Consider a set-associative cache of size 2 KB (1 KB = 210 bytes) with cache block size of 64 bytes. Assume that the cache is byte-addressable and a 32...

A direct mapped cache memory of 1 MB has a block ize of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it...

The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by ...

A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable an...

A $$32$$-bit wide main memory unit with a capacity of $$1$$ $$GB$$ is built using $$256M\,\, \times \,\,4$$-bit $$DRAM$$ chips. The number of rows of ...

A processor can support a maximum memory of $$4$$ $$GB,$$ where the memory is word-addressable (a word consists of two bytes). The size of the address...

Assume that for a certain processor, a read request takes $$50$$ nanoseconds on a cache miss and $$5$$ nanoseconds on a cache hit. Suppose while runni...

Consider a machine with a byte addressable main memory of $${2^{20}}$$ bytes, block size of $$16$$ bytes and a direct mapped cache having $${2^{12}}$$...

An access sequence of cache block addresses is of length $$N$$ and contains $$n$$ unique block address. The number of unique block addresses between t...

In a $$k$$-way set associative cache, the cache is divided into $$v$$ sets, each of which consists of $$k$$ lines. The lines of a set are placed in se...

The amount of $$ROM$$ needed to implement a $$4$$ bit multiplier is

A main memory unit with a capacity of $$4$$ megabytes is built using $$1M \times 1$$-bit $$DRAM$$ chips. Each $$DRAM$$ chip has $$1K$$ rows of cells w...

How many $$32k$$ x $$1$$ $$RAM$$ chips are needed to provide a memory capacity of $$256$$ $$K$$-bytes?

Consider a $$4$$-way set associative cache consisting of $$128$$ lines with a line size of $$64$$ words. The $$CPU$$ generates a $$20$$-bit address of...

Increasing the $$RAM$$ of a computer typically improves performance because

More than one word are put in one cache block to

The main memory of a computer has $$2$$ $$cm$$ blocks while the cache has $$2$$ $$c$$ blocks. If the cache uses the set associative mapping scheme wit...

A $$ROM$$ is used to store the table for multiplication of two $$8$$ bit unsigned integers. The size of $$ROM$$ required is

A $$ROM$$ is used to store a truth table for a binary multiplier unit that will multiply two $$4$$ bit numbers. The size of the $$ROM$$ (number of wor...

The capacity of a memory unit is defined by the number of words multiplied by the number of bits/word. How many separate address and data lines are ne...

A computer system has a $$4K$$ word cache organized in block set associative manner with $$4$$ blocks per set, $$64$$ words per block. The number of b...

Consider two set-associative cache memory architectures: WBC, which uses the write back policy, and WTC, which uses the write through policy. Both of ...

A given program has 25% load/store instructions. Suppose the ideal CPI (cycles per instruction) without any memory stalls is 2. The program exhibits 2...

A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip s...

An 8-way set associative cache of size 64 KB (1 KB = 1024 bytes) is used in a system with 32-bit address. The address is sub-divided into TAG, INDEX, ...

Consider a computer system with a byte-addressable primary memory of size 232 bytes. Assume the computer system has a direct-mapped cache of size...

A computer system with a word length of 32 bits has a 16 MB byte-addressable main memory and a 64 KB, 4-way set associative cache memory with a block ...

The size of the physical address space of a processor is $${2^P}$$ bytes. The word length is $${2^W}$$ bytes. The capacity of cache memory is $${2^N}$...

The width of the physical address on a machine is $$40$$ bits. The width of the tag field in a $$512$$ $$KB$$ $$8$$-way set associative cache is _____...

A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the ca...

The memory access time is $$1$$ nanosecond for a read operation with a hit in cache, $$5$$ nanoseconds for a read operation with a miss in cache, $$2$...

A $$4$$-way set-associative cache memory unit with a capacity of $$16KB$$ is built using a block size of $$8$$ words. The word length is $$32$$ bits. ...

In designing a computer’s cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is corre...

If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to ...

Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the ...

A $$RAM$$ chip has a capacity of $$1024$$ words of $$8$$ bits each $$\left( {1K \times 8} \right).$$ The number of $$2 \times 4$$ decoders with enable...

A computer has a $$256$$ $$K$$ Byte, $$4$$-way set associative, write back data cache with block size of $$32$$ Bytes. The processor sends $$32$$ bit ...

A computer has a $$256$$ $$K$$ Byte, $$4$$-way set associative, write back data cache with block size of $$32$$ Bytes. The processor sends $$32$$ bit ...

An $$8KB$$ direct-mapped write-back cache is organized as multiple blocks, each of size $$32$$-bytes. The processor generates $$32$$-bit addresses. Th...

A computer system has an $$L1$$ cache, an $$L2$$ cache, and a main memory unit connected as shown below. The block size in $$L1$$ cache is $$4$$ words...

A computer system has an $$L1$$ cache, an $$L2$$ cache, and a main memory unit connected as shown below. The block size in $$L1$$ cache is $$4$$ words...

Consider a $$4$$-way set associative cache (initially empty) with total $$16$$ cache blocks. The main memory consists of $$256$$ blocks and the reques...

For inclusion to hold between two cache levels $$L1$$ and $$L2$$ in a multilevel cache hierarchy, which of the following are necessary? $$1.$$ $$L1$$ ...

Consider a machine with a byte addressable main memory of $${2^{16}}$$ bytes. Assume that a direct mapped data cache consisting of $$32$$ lines of $$6...

Consider a machine with a byte addressable main memory of $${2^{16}}$$ bytes. Assume that a direct mapped data cache consisting of $$32$$ lines of $$6...

A $$CPU$$ has a cache with block size $$64$$ bytes. The main memory has $$k$$ banks, each bank being $$c$$ bytes wide. Consecutive $$c$$-byte chunks a...

Consider two cache organization: The first one is $$32$$ $$KB$$ $$2$$-way set associate with $$32$$-byte block size. The second one is of the same siz...

Consider two cache organization: The first one is $$32$$ $$KB$$ $$2$$-way set associate with $$32$$-byte block size. The second one is of the same siz...

Consider a direct mapped cache of size $$32$$ $$KB$$ with block size $$32$$ bytes. The $$CPU$$ generates $$32$$ bit addresses. The number of bits need...

Consider a small two-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, uses the least recently used ...

A block -set associative cache memory consists of $$128$$ blocks divided into four block sets. The main memory consists of $$16,384$$ blocks and each ...

A $$CPU$$ has $$32$$-bit memory address and a $$256$$ $$KB$$ cache memory. The cache is organized as a $$4$$-way set associative cache with cache bloc...

A computer system has a three level memory hierarchy, with access time and hit ratios as shown below: (i) What should be the minimum size of leve...