1
GATE CSE 2000
MCQ (Single Correct Answer)
+2
-0.6
The following arrangement of master-slave flip-flop GATE CSE 2000 Digital Logic - Sequential Circuits Question 26 English

Has the initial state of $$P, Q$$ as $$0, 1$$ (respectively). After three clock cycles the output states $$P, Q$$ is (respectively).

A
$$1,0$$
B
$$1,1$$
C
$$0,0$$
D
$$0,1$$
2
GATE CSE 1991
Numerical
+2
-0
Find the maximum clock frequency at which the counter in Fig., can be operated. Assume that the propagation delay through each flip-flop and $$AND$$ gate is $$10$$ $$ns.$$ Also assume that the setup time for the $$JK$$ inputs of the flip-flops is negligible. GATE CSE 1991 Digital Logic - Sequential Circuits Question 27 English
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