IO Interface · Computer Organization · GATE CSE

Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?

Which one of the following statements is FALSE?

A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and consumes 100 $$\mu$$s (micro seconds) for each poll. If it is determined after polling that a key has been pressed, the system consumes an additional 200 $$\mu$$s to process the keystroke. Let $$T_1$$ denote the fraction of a second spent in polling and processing a keystroke.

In an alternative implementation, the system uses interrupts instead of polling. An interrupt is raised for every keystroke. It takes a total of 1 ms for servicing an interrupt and processing a keystroke. Let $$T_2$$ denote the fraction of a second spent in servicing the interrupt and processing a keystroke.

The ratio $${{{T_1}} \over {{T_2}}}$$ is __________. (Rounded off to one decimal place)

Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?

$$ * \,\,\,\,\,\,\,\,\,\,\,$$ Interrupt from $$CPU$$ temperature sensor (raises interrupt if $$CPU$$
$$\,\,\,\,\,\,\,\,\,\,\,\,\,\,$$ temperature is too high)
$$ * \,\,\,\,\,\,\,\,\,\,\,$$ Interrupt from Mouse (raises interrupt if the mouse is moved or a button is
$$\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,$$pressed)
$$ * \,\,\,\,\,\,\,\,\,\,\,$$ Interrupt from Keyboard (raises interrupt when a key is pressed or released)
$$ * \,\,\,\,\,\,\,\,\,\,\,$$ Interrupt from Hard Disk (raises interrupt when a disk read is completed)

Which one of these will be handled at the $$HIGHEST$$ priority?

$$(P)$$ The processor pushes the process status of $$L$$ onto the control stack.
$$(Q)$$ The processor finishes the execution of the current instruction.
$$(R)$$ The processor executes the interrupt service routine.
$$(S)$$ The processor pops the process status of $$L$$ from the control stack.
$$(T)$$ The processor loads the new PC value based on the interrupt.

Which one of the following is the correct order in which the events above occur?

Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is non- load/store instruction. The load-store instructions take two clock cycles to execute.

The designer of the system also has an alternate approach of using the $$DMA$$ controller to implement the same transfer. The $$DMA$$ controller requires $$20$$ clock cycles for initialization and other overheads. Each $$DMA$$ transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.

What is the approximate speed up when the $$DMA$$ controller based design is used in place of the interrupt driven program based input-output?