1
GATE CSE 2026 Set 1
MCQ (Single Correct Answer)
+2
-0

Consider a 2-bit saturating up/down counter that performs the saturating up count when the input $P$ is 0 , and the saturating down count when $P$ is 1 . The Next State table of the counter is as shown. The counter is built as a synchronous sequential circuit using $D$ flip-flops.

Inpur Current state Next state
$$
P
$$
$$
Q_1
$$
$$
Q_0
$$
$$
Q_1^{+}
$$
$$
Q_0^{+}
$$
$$
\begin{aligned}
& 0 \\
& 0 \\
& 0 \\
& 0 \\
& 1 \\
& 1 \\
& 1 \\
& 1
\end{aligned}
$$
$$
\begin{aligned}
& 0 \\
& 0 \\
& 1 \\
& 1 \\
& 0 \\
& 0 \\
& 1 \\
& 1
\end{aligned}
$$
$$
\begin{aligned}
& 0 \\
& 1 \\
& 0 \\
& 1 \\
& 0 \\
& 1 \\
& 0 \\
& 1
\end{aligned}
$$
$$
\begin{aligned}
& 0 \\
& 1 \\
& 1 \\
& 1 \\
& 0 \\
& 0 \\
& 0 \\
& 1
\end{aligned}
$$
$$
\begin{aligned}
& 1 \\
& 0 \\
& 1 \\
& 1 \\
& 0 \\
& 0 \\
& 1 \\
& 0
\end{aligned}
$$
Which one of the following options corresponds to the expressions for the inputs of the $D$ flip-flops, $D_1$ and $D_0$ ?
A

$D_1=P Q_1+\bar{P} Q_0+Q_1 Q_0 \quad D_0=P Q_0+\bar{P} Q_1+Q_1 \overline{Q_0}$

B

$D_1=\bar{P} Q_1+\bar{P} Q_0+Q_1 Q_0 \quad D_0=\bar{P} \overline{Q_0}+\bar{P} Q_1+Q_1 \overline{Q_0}$

C

$D_1=\bar{P} \bar{Q}_1+\bar{P} Q_0+Q_1 Q_0 \quad D_0=\bar{P} Q_0+\bar{P} Q_1+Q_1 \overline{Q_0}$

D

$D_1=P \overline{Q_1}+\bar{P} Q_0+Q_1 Q_0 \quad D_0=P \overline{Q_0}+\bar{P} Q_1+Q_1 \overline{Q_0}$

2
GATE CSE 2025 Set 1
Numerical
+2
-0

Consider the given sequential circuit designed using D-Flip-flops. The circuit is initialized with some value (initial state). The number of distinct states the circuit will go through before returning back to the initial state is _________ . (Answer in integer)

GATE CSE 2025 Set 1 Digital Logic - Sequential Circuits Question 3 English

Your input ____
3
GATE CSE 2023
MCQ (Single Correct Answer)
+2
-0.67

Consider a sequential digital circuit consisting of T flip-flops and D flip-flops as shown in the figure. CLKIN is the clock input to the circuit. At the beginning, Q1, Q2 and Q3 have values 0, 1 and 1, respectively.

GATE CSE 2023 Digital Logic - Sequential Circuits Question 4 English

Which one of the given values of (Q1, Q2, Q3) can NEVER be obtained with this digital circuit?

A
(0, 0, 1)
B
(1, 0, 0)
C
(1, 0, 1)
D
(1, 1, 1)
4
GATE CSE 2022
MCQ (Single Correct Answer)
+2
-0.67

Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word is used to load a word in X, either from S or from R. S is a 1024-word memory segment and R is a 32-word register file. Based on the value of mode bit M, T selects an input word to load in X. P and Q interface with the corresponding bits in the code word to choose the addressed word. Which one of the following represents the functionality of P, Q, and T?

GATE CSE 2022 Digital Logic - Sequential Circuits Question 6 English

A
P is 10 : 1 multiplexer; Q is 5 : 1 multiplexer; T is 2 : 1 multiplexer
B
P is 10 : 210 decoder; Q is 5 : 25 decoder; T is 2 : 1 encoder
C
P is 10 : 210 decoder; Q is 5 : 25 decoder; T is 2 : 1 multiplexer
D
P is 1 : 10 de-multiplexer; Q is 1 : 5 de-multiplexer; T is 2 : 1 multiplexer

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