1
GATE CSE 1991
Numerical
+2
-0
Find the maximum clock frequency at which the counter in Fig., can be operated. Assume that the propagation delay through each flip-flop and $$AND$$ gate is $$10$$ $$ns.$$ Also assume that the setup time for the $$JK$$ inputs of the flip-flops is negligible.
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Questions Asked from Sequential Circuits (Marks 2)
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GATE CSE Subjects
Discrete Mathematics
Programming Languages
Theory of Computation
Operating Systems
Computer Organization
Database Management System
Data Structures
Computer Networks
Algorithms
Compiler Design
Software Engineering
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General Aptitude