1
GATE CSE 2007
+2
-0.6
The control signal functions of a $$4$$-bit binary counter are given below $$($$where $$X$$ “don’t care”$$):$$ The counter is connected as follows: Assume that the counter and gate delays are negligible. If the counter starts at $$0,$$ then it cycles through the following sequence:

A
$$0, 3, 4$$
B
$$0, 3, 4, 5$$
C
$$0, 1, 2, 3, 4$$
D
$$0, 1, 2, 3, 4, 5$$
2
GATE CSE 2006
+2
-0.6
Consider the circuit in the diagram. The $$\oplus$$ operator represents $$EX$$-$$OR.$$ The $$D$$ flip-flops are initialized to zeros (cleared). The following data: $$100110000$$ is supplied to the ''data'' terminal in nine clock cycles. After that the values of $${q_2}{q_1}{q_0}$$ are

A
$$000$$
B
$$001$$
C
$$010$$
D
$$101$$
3
GATE CSE 2004
+2
-0.6
Consider the partial implementation of a $$2$$-bit counter using $$T$$ flip-flops following the sequence $$0$$-$$2$$-$$3$$-$$1$$-$$0,$$ as shown below. To complete the circuit, the input $$X$$ should be

A
$${Q_2}$$
B
$${Q_2} + {Q_1}$$
C
$$\left( {{Q_1} \oplus {Q_2}} \right)'$$
D
$$\left( {{Q_1} \oplus {Q_2}} \right)$$
4
GATE CSE 2003
+2
-0.6
A 1- input, 2- output synchronous sequential circuit behaves as follows.

Let $${z_k},\,{n_k}$$ denote the number of $$0’s$$ and $$1’s$$ respectively in initial $$k$$ bits of the input

$$\left({{z_k} + {n_k} = k} \right).$$ The circuit outputs $$00$$ until one of the following conditions holds.

$$* \,\,\,\,\,$$ $${z_k} = {n_k} + 2.\,\,\,$$ In this case, the output at the $$k$$-th and all subsequent clock ticks is $$10.$$

$$* \,\,\,\,\,$$ $${n_k} = {z_k} + 2.\,\,\,$$ In this case, the output at the $$k$$-th and all subsequent clock ticks is $$01.$$

What is the minimum number of states required in the state transition graph of the above circuit?

A
$$5$$
B
$$6$$
C
$$7$$
D
$$8$$
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