1
GATE CSE 2003
MCQ (Single Correct Answer)
+2
-0.6
A 1- input, 2- output synchronous sequential circuit behaves as follows.

Let $${z_k},\,{n_k}$$ denote the number of $$0’s$$ and $$1’s$$ respectively in initial $$k$$ bits of the input

$$\left({{z_k} + {n_k} = k} \right).$$ The circuit outputs $$00$$ until one of the following conditions holds.

$$ * \,\,\,\,\,$$ $${z_k} = {n_k} + 2.\,\,\,$$ In this case, the output at the $$k$$-th and all subsequent clock ticks is $$10.$$

$$ * \,\,\,\,\,$$ $${n_k} = {z_k} + 2.\,\,\,$$ In this case, the output at the $$k$$-th and all subsequent clock ticks is $$01.$$

What is the minimum number of states required in the state transition graph of the above circuit?

A
$$5$$
B
$$6$$
C
$$7$$
D
$$8$$
2
GATE CSE 2001
MCQ (Single Correct Answer)
+2
-0.6
Consider the circuit given below with initial state $${Q_0} = 1,\,\,{Q_1} = {Q_2} = 0.$$ The state of the circuit is given by the value of $$4{Q_2} + 2{Q_1} + {Q_{0.}}$$ GATE CSE 2001 Digital Logic - Sequential Circuits Question 25 English

Which one of the following is correct state sequence of the circuit?

A
$$1,3,4,6,7,5,2$$
B
$$1, 2, 5, 3, 7, 6, 4$$
C
$$1, 2, 7, 3, 5, 6, 4$$
D
$$1, 6, 5, 7, 2, 3, 4$$
3
GATE CSE 2001
MCQ (Single Correct Answer)
+2
-0.6
Consider the following circuit with initial state $${Q_0} = {Q_1} = 0.$$ The $$D$$ Flip-Flops are positive edge triggered and have set up times $$20$$ nanosecond and hold times $$0.$$ GATE CSE 2001 Digital Logic - Sequential Circuits Question 18 English 1

Consider the following timing diagram of $$X$$ and $$C;$$ the clock period of $$C>40$$ nanosecond which one is the correct plot of $$Y?$$

GATE CSE 2001 Digital Logic - Sequential Circuits Question 18 English 2
A
GATE CSE 2001 Digital Logic - Sequential Circuits Question 18 English Option 1
B
GATE CSE 2001 Digital Logic - Sequential Circuits Question 18 English Option 2
C
GATE CSE 2001 Digital Logic - Sequential Circuits Question 18 English Option 3
D
GATE CSE 2001 Digital Logic - Sequential Circuits Question 18 English Option 4
4
GATE CSE 2000
MCQ (Single Correct Answer)
+2
-0.6
The following arrangement of master-slave flip-flop GATE CSE 2000 Digital Logic - Sequential Circuits Question 26 English

Has the initial state of $$P, Q$$ as $$0, 1$$ (respectively). After three clock cycles the output states $$P, Q$$ is (respectively).

A
$$1,0$$
B
$$1,1$$
C
$$0,0$$
D
$$0,1$$
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