1
GATE CSE 2011
MCQ (Single Correct Answer)
+2
-0.6
Consider the following circuit involving three Dtypes flip-flops used in a certain type of Counter configuration. GATE CSE 2011 Digital Logic - Sequential Circuits Question 19 English

If all the flip-flops were reset to $$0$$ at power on, what is the total number of distinct outputs (states) represented by $$PQR$$ generated by the counter?

A
$$3$$
B
$$4$$
C
$$5$$
D
$$6$$
2
GATE CSE 2009
MCQ (Single Correct Answer)
+2
-0.6
Given the following state table of an $$FSM$$ with two states $$A$$ and $$B,$$ one input and one output: GATE CSE 2009 Digital Logic - Sequential Circuits Question 20 English

If the initial state is $$A = 0, B=0.$$ What is the minimum length of an input string which will take the machine to the state $$A=0, B=1$$ with Output$$=1?$$

A
$$3$$
B
$$4$$
C
$$5$$
D
$$6$$
3
GATE CSE 2007
MCQ (Single Correct Answer)
+2
-0.6
The control signal functions of a $$4$$-bit binary counter are given below $$($$where $$X$$ “don’t care”$$):$$ GATE CSE 2007 Digital Logic - Sequential Circuits Question 21 English 1

The counter is connected as follows:

GATE CSE 2007 Digital Logic - Sequential Circuits Question 21 English 2

Assume that the counter and gate delays are negligible. If the counter starts at $$0,$$ then it cycles through the following sequence:

A
$$0, 3, 4$$
B
$$0, 3, 4, 5$$
C
$$0, 1, 2, 3, 4$$
D
$$0, 1, 2, 3, 4, 5$$
4
GATE CSE 2006
MCQ (Single Correct Answer)
+2
-0.6
Consider the circuit in the diagram. The $$ \oplus $$ operator represents $$EX$$-$$OR.$$ The $$D$$ flip-flops are initialized to zeros (cleared). GATE CSE 2006 Digital Logic - Sequential Circuits Question 13 English

The following data: $$100110000$$ is supplied to the ''data'' terminal in nine clock cycles. After that the values of $${q_2}{q_1}{q_0}$$ are

A
$$000$$
B
$$001$$
C
$$010$$
D
$$101$$
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