NEW
New Website Launch
Experience the best way to solve previous year questions with mock tests (very detailed analysis), bookmark your favourite questions, practice etc...
1

### GATE CSE 2011

Consider the following circuit involving three Dtypes flip-flops used in a certain type of Counter configuration.

If all the flip-flops were reset to $$0$$ at power on, what is the total number of distinct outputs (states) represented by $$PQR$$ generated by the counter?

A
$$3$$
B
$$4$$
C
$$5$$
D
$$6$$
2

### GATE CSE 2011

Consider the following circuit involving three Dtypes flip-flops used in a certain type of Counter configuration.

If at some instance prior to the occurrence of the clock edge, $$P, Q$$ and $$R$$ have a value $$0,1$$ and $$0$$ respectively, what shall be the value of $$PQR$$ after the clock edge?

A
$$000$$
B
$$001$$
C
$$010$$
D
$$011$$
3

### GATE CSE 2009

Given the following state table of an $$FSM$$ with two states $$A$$ and $$B,$$ one input and one output:

If the initial state is $$A = 0, B=0.$$ What is the minimum length of an input string which will take the machine to the state $$A=0, B=1$$ with Output$$=1?$$

A
$$3$$
B
$$4$$
C
$$5$$
D
$$6$$
4

### GATE CSE 2007

The control signal functions of a $$4$$-bit binary counter are given below $$($$where $$X$$ “don’t care”$$):$$

The counter is connected as follows:

Assume that the counter and gate delays are negligible. If the counter starts at $$0,$$ then it cycles through the following sequence:

A
$$0, 3, 4$$
B
$$0, 3, 4, 5$$
C
$$0, 1, 2, 3, 4$$
D
$$0, 1, 2, 3, 4, 5$$
Write for Us

Do you want to write for us? Help us by contributing to our platform.

### Joint Entrance Examination

JEE Main JEE Advanced WB JEE

### Graduate Aptitude Test in Engineering

GATE CSE GATE ECE GATE EE GATE ME GATE CE GATE PI GATE IN

NEET

Class 12