GATE CSE 2024 Set 1 | Combinational Circuits Question 1 | Digital Logic

GATE CSE 2024 Set 1

MCQ (More than One Correct Answer)

-0

Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires have no delays. Which of the following statements about the circuit is/are CORRECT?

GATE CSE 2024 Set 1 Digital Logic - Combinational Circuits Question 2 English

With no propagation delays, the output Y is always logic Zero

With no propagation delays, the output Y is always logic One

With propagation delays, the output Y can have a transient logic One after X transitions from logic Zero to logic One

With propagation delays, the output Y can have a transient logic Zero after X transitions from logic One to logic Zero

GATE CSE 2021 Set 2

MCQ (Single Correct Answer)

-0.33

Which one of the following circuits implements the Boolean function given below?

f(x, y, z) = m₀ + m₁ + m₃ + m₄ + m₅ + m₆, where m_i is the i^th minterm.

GATE CSE 2021 Set 2 Digital Logic - Combinational Circuits Question 4 English Option 1

GATE CSE 2021 Set 2 Digital Logic - Combinational Circuits Question 4 English Option 2

GATE CSE 2021 Set 2 Digital Logic - Combinational Circuits Question 4 English Option 3

GATE CSE 2021 Set 2 Digital Logic - Combinational Circuits Question 4 English Option 4

GATE CSE 2020

Numerical

-0

A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is _____.

Your input ____

GATE CSE 2020

Numerical

-0

If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m + n is ____.

Your input ____