GATE CSE
Digital Logic
Sequential Circuits
Previous Years Questions

## Marks 1

Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word is used to load a word in X, ...
Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered $$D$$ flip-flops. The number of states i...
We want to design a synchronous counter that counts the sequence $$0-1-0-2-0-3$$ and then repeats. The minimum number of $$J-K$$ flip-flops required t...
The minimum number of $$JK$$ flip-flops required to construct a synchronous counter with the count sequence $$\left( {0,0,1,1,2,2,3,3,0,0,...} \right)... Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is Let$$k = {2^n}.$$A circuit is built by giving the output of an ݊$$n$$-bit binary counter as input to an$$n$$-to-$${2^n}$$bit decoder. This circui... You are given a free running clock with a duty cycle of$$50$$% and a digital waveform$$f$$which changes only at the negative edge of the clock. Whi...$$SR.$$latch made by cross coupling two$$NAND$$gates if$$S=R=0,$$Then it will result in ## Marks 2 Consider a 3-bit counter, designed using T flip-flop, as shown below: Assuming the initial state of the counter given by PQR as 000, what are th... A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected ... The above synchronous sequential circuit built using$$JK$$flip-flops is initialized with$${Q_2}{Q_1}{Q_0} = 000.\,\,$$The state sequence for this... Consider the following circuit involving three Dtypes flip-flops used in a certain type of Counter configuration. If all the flip-flops were reset t... Consider the following circuit involving three Dtypes flip-flops used in a certain type of Counter configuration. If at some instance prior to the o... Given the following state table of an$$FSM$$with two states$$A$$and$$B,$$one input and one output: If the initial state is$$A = 0, B=0.$$What... The control signal functions of a$$4$$-bit binary counter are given below$$($$where$$X$$“don’t care”$$):$$The counter is connected as follows: ... Consider the circuit in the diagram. The$$ \oplus $$operator represents$$EX$$-$$OR.$$The$$D$$flip-flops are initialized to zeros (cleared). T... Consider the partial implementation of a$$2$$-bit counter using$$T$$flip-flops following the sequence$$0$$-$$2$$-$$3$$-$$1$$-$$0,$$as shown belo... A 1- input, 2- output synchronous sequential circuit behaves as follows. Let$${z_k},\,{n_k}$$denote the number of$$0’s$$and$$1’s$$respectively i... Consider the circuit given below with initial state$${Q_0} = 1,\,\,{Q_1} = {Q_2} = 0.$$The state of the circuit is given by the value of$$4{Q_2} + ...
Consider the following circuit with initial state $${Q_0} = {Q_1} = 0.$$ The $$D$$ Flip-Flops are positive edge triggered and have set up times $$20$$...
The following arrangement of master-slave flip-flop Has the initial state of $$P, Q$$ as $$0, 1$$ (respectively). After three clock cycles the output...
Find the maximum clock frequency at which the counter in Fig., can be operated. Assume that the propagation delay through each flip-flop and $$AND$$ g...

## Marks 5

Consider the synchronous sequential circuit in fig. (a) Draw a state diagram which is implemented by the circuit. Use the following names for the st...
For the synchronous counter shown in fig. write the truth table of $${Q_0},\,\,{Q_1}$$ and $${Q_2}$$ after each pulse starting from {Q_0} = {Q_1} = ...
EXAM MAP
Joint Entrance Examination