# Sequential Circuits · Digital Logic · GATE CSE

Start Practice## Marks 1

GATE CSE 2022

Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word is used to load a word in X, ...

GATE CSE 2018

Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered $$D$$ flip-flops.
The number of states i...

GATE CSE 2016 Set 1

We want to design a synchronous counter that counts the sequence $$0-1-0-2-0-3$$ and then repeats. The minimum number of $$J-K$$ flip-flops required t...

GATE CSE 2015 Set 1

Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is

GATE CSE 2015 Set 2

The minimum number of $$JK$$ flip-flops required to construct a synchronous counter with the count sequence $$\left( {0,0,1,1,2,2,3,3,0,0,...} \right)...

GATE CSE 2014 Set 2

Let $$k = {2^n}.$$ A circuit is built by giving the output of an ݊$$n$$-bit binary counter as input to an $$n$$-to-$${2^n}$$ bit decoder. This circui...

GATE CSE 2006

You are given a free running clock with a duty cycle of $$50$$% and a digital waveform $$f$$ which changes only at the negative edge of the clock. Whi...

GATE CSE 2004

$$SR.$$ latch made by cross coupling two $$NAND$$ gates if $$S=R=0,$$ Then it will result in

## Marks 2

GATE CSE 2021 Set 1

Consider a 3-bit counter, designed using T flip-flop, as shown below:
Assuming the initial state of the counter given by PQR as 000, what are th...

GATE CSE 2015 Set 1

A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected ...

GATE CSE 2014 Set 3

The above synchronous sequential circuit built using $$JK$$ flip-flops is initialized with $${Q_2}{Q_1}{Q_0} = 000.\,\,$$ The state sequence for this...

GATE CSE 2011

Consider the following circuit involving three Dtypes flip-flops used in a certain type of Counter configuration.
If all the flip-flops were reset t...

GATE CSE 2011

Consider the following circuit involving three Dtypes flip-flops used in a certain type of Counter configuration.
If at some instance prior to the o...

GATE CSE 2009

Given the following state table of an $$FSM$$ with two states $$A$$ and $$B,$$ one input and one output:
If the initial state is $$A = 0, B=0.$$ What...

GATE CSE 2007

The control signal functions of a $$4$$-bit binary counter are given below $$($$where $$X$$ “don’t care”$$):$$
The counter is connected as follows:
...

GATE CSE 2006

Consider the circuit in the diagram. The $$ \oplus $$ operator represents $$EX$$-$$OR.$$ The $$D$$ flip-flops are initialized to zeros (cleared).
T...

GATE CSE 2004

Consider the partial implementation of a $$2$$-bit counter using $$T$$ flip-flops following the sequence $$0$$-$$2$$-$$3$$-$$1$$-$$0,$$ as shown belo...

GATE CSE 2003

A 1- input, 2- output synchronous sequential circuit behaves as follows.
Let $${z_k},\,{n_k}$$ denote the number of $$0’s$$ and $$1’s$$ respectively i...

GATE CSE 2001

Consider the circuit given below with initial state $${Q_0} = 1,\,\,{Q_1} = {Q_2} = 0.$$ The state of the circuit is given by the value of $$4{Q_2} + ...

GATE CSE 2001

Consider the following circuit with initial state $${Q_0} = {Q_1} = 0.$$ The $$D$$ Flip-Flops are positive edge triggered and have set up times $$20$$...

GATE CSE 2000

The following arrangement of master-slave flip-flop
Has the initial state of $$P, Q$$ as $$0, 1$$ (respectively). After three clock cycles the output...

GATE CSE 1991

Find the maximum clock frequency at which the counter in Fig., can be operated. Assume that the propagation delay through each flip-flop and $$AND$$ g...

## Marks 5

GATE CSE 1996

Consider the synchronous sequential circuit in fig.
(a) Draw a state diagram which is implemented by the circuit. Use the following names for the st...

GATE CSE 1990

For the synchronous counter shown in fig. write the truth table of $${Q_0},\,\,{Q_1}$$ and $${Q_2}$$ after each pulse starting from $${Q_0} = {Q_1} = ...