Consider the following circuit with initial state $${Q_0} = {Q_1} = 0.$$ The $$D$$ Flip-Flops are positive edge triggered and have set up times $$20$$ nanosecond and hold times $$0.$$

Consider the following timing diagram of $$X$$ and $$C;$$ the clock period of $$C>40$$ nanosecond which one is the correct plot of $$Y?$$

The following arrangement of master-slave flip-flop

Has the initial state of $$P, Q$$ as $$0, 1$$ (respectively). After three clock cycles the output states $$P, Q$$ is (respectively).

Find the maximum clock frequency at which the counter in Fig., can be operated. Assume that the propagation delay through each flip-flop and $$AND$$ gate is $$10$$ $$ns.$$ Also assume that the setup time for the $$JK$$ inputs of the flip-flops is negligible.