1
GATE EE 2015 Set 1
Numerical
+2
-0
The figure shows a digital circuit constructed using negative edge triggered $$J-K$$ flip flops. Assume a starting state of $${Q_2}\,{Q_1}\,{Q_0} = 000.$$ This state $${Q_2}\,{Q_1}\,{Q_0} = 000$$ will repeat after _____ number of cycles of the clock $$CLK.$$
Your input ____
2
GATE EE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
A $$JK$$ flip flop can be implemented by $$T$$ flip flops. Identify the correct implementation.
3
GATE EE 2013
MCQ (Single Correct Answer)
+2
-0.6
The clock frequency applied to the digital circuit shown in the figure below is $$1$$ $$kHz.$$ If the initial state of the output $$Q$$ of the flip-flop is $$‘0’,$$ then the frequency of the output waveform $$Q$$ in $$kHz$$ is
4
GATE EE 2012
MCQ (Single Correct Answer)
+2
-0.6
The state transition diagram for the logic circuit shown is
Questions Asked from Sequential Circuits (Marks 2)
Number in Brackets after Paper Indicates No. of Questions
GATE EE Subjects
Electric Circuits
Electromagnetic Fields
Signals and Systems
Electrical Machines
Engineering Mathematics
General Aptitude
Power System Analysis
Electrical and Electronics Measurement
Analog Electronics
Control Systems
Power Electronics